STEL-1209/CE Intel, STEL-1209/CE Datasheet
STEL-1209/CE
Related parts for STEL-1209/CE
STEL-1209/CE Summary of contents
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... KEY FEATURES n Evaluation tool for STEL-1109 digital modulator ASICs n Burst or continuous BPSK, QPSK, 16QAM modulator at rates Msps n On-board or external clock capability – 165 MHz MHz output frequency n High frequency resolution – 24 bits 165 MHz n Digitally filtered data results in low modulation side lobes – ...
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... Current drawn on the -5 volt supply is 10 mA. There are two 5 volt to 3.3 volt converters on the board and the design serves to demonstrate the inter-operability of the STEL-1109 volt or 3.3 volt system. The STEL- 1109 ASIC, which is a 3.3V device, consumes 1.8 mA/MHz in continuous mode. Current consumption by the ASIC can be easily measured by connecting pin 2 of JP9 (see package outline ...
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... CLK Note: The on-board low pass filter (LPF) cut-off frequency can be selected between 42 MHz or 65 MHz by properly configuring JP5 and JP6. STEL-1209 J1 -- External Serial Data Input: BNC connector, HCMOS levels. Output Level Control: The output level can be controlled over a range steps by means of the control software supplied ...
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... ORDERING INFORMATION To order, specify Model Number STEL-1209/CE. “CE” indicates a commercial grade, board-level product. PACKAGE OUTLINE Reset U2 S1 EPROM J8 SYNC J1 EXT DATA U11 J6 Xtal. EXT DATA CLK Osc. J2 MASTER CLK JP4 J5 BURST GATE J16 JP8 EXT TCLK 6.3" (16 cm) MOLEX 4455C-A ...
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... STEL-9244. However still necessary to have a good understanding of the capability of both the STEL- 1209 and the STEL-1109 to be able to use this software tool effectively. Standard Windows 95 procedures are used in operating the menus and controls. Many of the buttons require only a single click to activate ...
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... The Note that the sum of the lengths of the preamble, packet size, and guard time must not exceed 16384. Preamble Size STEL-1209's preamble size is programmable between 0 and 255 symbols. Packet Size Minimum packet length is one and maximum packet length is given by Packet Length(max) = 16383 - Guard Time - Preamble ...
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... This controls the attenuator on the STEL-1209 board steps, from dB. Freeze NCO SIN output This button collapses the constellation onto the I axis. It can be used in BPSK mode to rotate the constellation by 45°. Invert Spectrum The output of the I- and Q-channel adder block in the STEL-1109 normally provides an output of the form Icos(wt) + Qsin(wt) ...
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... Scrambler engine can also be turned on by selecting the S/W Control and Enable buttons. Differential Encoder Enable DIFFEN signal can be used to tell the STEL-1109 to turn on the Diff. Encoder engine. This is the H/W Control method and the corresponding button should be selected. Without using the DIFFEN signal, the Diff. ...
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... STEL-1209 14 ...
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... FILTERS SCREEN The STEL-1109 provides a total of 32 taps for the FIR filter coefficients. The FIR filter architecture as provided calls for a symmetrical number of taps; thus, one only needs to enter the FIR coefficients 16 times. FIR AND INTERPOLATION FILTER FIR Filter Bypass This button allows the user data to bypass FIR filter processing ...
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... JP1 Com1 STEL-1209 Interpolation Stages The number of interpolation stages used in the STEL- 1109 can be varied from means of this field. Three stages should be used whenever possible, to minimize spur levels. However, it may be necessary to use fewer than three stages when the data rate is very slow relative to the master clock frequency ...
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... RDSLEN goes low on the rising edge of TCLK (last user data symbol). (N) SCRMEN goes low on the rising edge of TCLK (on the cycle of TCLK after the last user data bit). (F) (B) (C) (D) (E) (L) (L) Preamble User Data 17 (G) (J) (I) (K) (H) (M) (N) Guard Time WCP 52934.c -5/7/97 H STEL-1209 to ...
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... RDSLEN SCRMEN SYMPLS DATAENO NOTE 1: STEL receivers differentially decode relative to the last preamble symbol. To encode the first symbol against a "zero" symbol reference instead, bring DIFFEN high at the leading edge of the user data packet (dotted line). NOTE 2: If bit 6 of Configuration Register 36 delayed by eight cycles of BITCLK (dotted line) ...
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... RDSLEN SCRMEN SYMPLS DATAENO NOTE 1: STEL receivers differentially decode relative to the last preamble symbol. To encode the first symbol against a "zero" symbol reference instead, bring DIFFEN high at the leading edge of the user data packet (dotted line). NOTE 2: If bit 6 of Configuration Register 36 delayed by eight cycles of BITCLK (dotted line) ...
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... RDSLEN SCRMEN SYMPLS DATAENO NOTE 1: STEL receivers differentially decode relative to the last preamble symbol. To encode the first symbol against a "zero" symbol reference instead, bring DIFFEN high at the leading edge of the user data packet (dotted line). NOTE 2: If bit 6 of Configuration Register 36 delayed by eight cycles of BITCLK (dotted line) ...
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... BER Tester Power Supply -5V @10 mA GND MOLEX 4455C-A U3 -5V Micro JP9 U5 * STEL- 1109 U19 * Burst Controller J3 STEL 9257 Burst Receiver STEL-1209 Default Setting: 1. Place All Jumpers As Shown With The 21 PC +5V @330 mA RS232 P2: 9‘D’ JP1 + JP3 * JP5 JP7 * U8 JP6 ...
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... STEL-1209 IC PARTS LIST Reference Designator U8 U15 U18 U7,U17 T1 U20 U4 U16 U2 U1 U10 U3 U19 Part Number AT17C256 CLC404AJE AT-210 LT1117CST T1-6T-KK81 IDT6116SA35SO MAX707CSA MAX232CSE 27C256-120JC MC74HC573ADW 74LVT14D P80C32EBA EPF81188AQC240-4 Manufacture Atmel Comlinear M/A-COM Linear Technology Mini-Circuit IDT Maxim Maxim AMD Motorola Philips ...
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WCP 970092A ...