STE10-100A STMicroelectronics, STE10-100A Datasheet - Page 42

• Manufacturer Part Number: STE10-100A
• Description: Pci 10/100 Ethernet Controller With Integrated Phy
• Manufacturer: STMicroelectronics

Registers and descriptors description
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Table 8.
CSR5 (offset = 28h), SR - Status register
31~ 26
25~ 23
22~ 20
19~17
Bit #
16
Control/status register description (continued)
Name
NISS
BET
----
RS
TS
Reserved
Bus error type. This field is valid only when bit 13
of CSR5(fatal bus error) is set. There is no
interrupt generated by this field.
000: parity error, 001: master abort, 010:
target abort
011, 1xx: reserved
Transmit state. Reports the current transmission
state only, no interrupt will be generated.
000: stop
001: read descriptor
010: transmitting
011: FIFO fill, read the data from memory and
put into FIFO
100: reserved
101: reserved
110: suspended, unavailable transmit descriptor
or FIFO overflow
111: write descriptor
Receive state. Reports current receive state
only, no interrupt will be generated.
000: stop
001: read descriptor
010: check this packet and pre-fetch next
descriptor
011: wait for receiving data
100: suspended
101: write descriptor
110: flush the current FIFO
111: FIFO drain, move data from receiving FIFO
into memory
Normal interrupt status summary. Set if any of
the following bits of CSR5 are asserted:
–
–
–
TCI, transmit completed interrupt (bit
0)
TDU, transmit descriptor unavailable
(bit 2)
RCI, receive completed interrupt (bit
6)
Description
Default
000
000
000
0
STE10/100A
RW type
RO/LH*
RO
RO
RO