RS8234 Mindspeed Technologies, RS8234 Datasheet
RS8234
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RS8234 Summary of contents
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... The ServiceSAR Controller generates and terminates ATM traffic as well as automatically scheduling cells for transmission. The RS8234 is targeted at 155 Mbps throughput systems where the number of VCCs is relatively large, or the performance of the overall system is critical. Examples of such networking equipment include Routers, Ethernet switches, ATM Edge switches, or Frame Relay switches ...
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... Ordering Information Model Number RS8234 Revision History © 1998-2003, Mindspeed Technologies™, a Conexant business All Rights Reserved. Information in this document is provided in connection with Mindspeed Technologies (“Mindspeed”) products. These materials are provided by Mindspeed as a service to its customers and may be used for informational purposes only. Mindspeed assumes no responsibility for errors or omissions in these materials ...
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... Revision Level A Advance N8234DS1B RS8234 Rev Revision 500413A Revision 28234-DSH-001-A Revision 28234-DSH-001-B Revision 28234-DSH-001-B Date July 1998 Created. All changes to the device up through Rev. C are included in this document. Specifically; increase in number of scheduling priorities, increased number of allowed VBR/ABR priorities, added scheduler control register, ...
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... Multi-Queue Segmentation Processing The RS8234’s segmentation coprocessor generates ATM cells for VCCs at a line rate 200 Mbps for simplex connections. The segmentation coprocessor formats cells on each channel according to segmentation VCC Tables, utilizing independent transmit queues and reporting segmentation status on a parallel set segmentation status queues ...
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... Per-VCC buffer firewall (memory usage limit) • Simultaneous reassembly and segmentation • Idle cell filtering • duplex VCCs Mindspeed Technologies ™ High Performance Host Architecture with Buffer Isolation • Write-only control and status • Read multiple command for data transfer • ...
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... LANE) • One programmable Interval Timer (32 bits w/ interrupt) • per-VCC AAL3/4 MIB counters: – # cells w/ CRC10 errors – # cells w/ MID errors – # cells w/ LI errors – # cells w/ SN errors – # cells w/ BOM or SSM errors – # cells w/ EOM errors Mindspeed Technologies ™ ...
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... Mindspeed Technologies ™ ...
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... Mindspeed Technologies ™ ...
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... Transmit Queues. These entries can be thought of as task lists for the ServiceSAR to perform. The RS8234 reports segmentation and reassembly status to the host by writing entries to segmentation and reassembly status queues, which the host then further processes ...
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... RS8234 Product Overview 1.1 Introduction The RS8234 host interface provides for control of host congestion through the following mechanisms. First, each peer maintains separate control and status queues. Then, each VCC in a peer group may be limited to a specific maximum receive buffer utilization, further controlling congestion. EPD is supported for VCCs that exceed their resource allotments ...
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... Frame Relay Interworking The VBR traffic category includes rate-shaping via the dual leaky bucket Generic Cell Rate Algorithm (GCRA) based on the Cell Loss Priority (CLP) bit, for use in Frame Relay. The RS8234 also implements the Frame Relay discard attribute by 28234-DSH-001-B 1.2 Service-Specific Performance Accelerators ...
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... CBR segmentation to an external rate (the host rate). The user can direct the RS8234 to segment traffic from a fixed PCI address (i.e., a Virtual FIFO) for circuit-based CBR traffic. The user can delineate up to sixteen CBR pipes (or tunnels) in which to transmit multiple UBR, VBR, or ABR channels ...
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... The RS8234 allows rate adjustments due to Use-It-Or-Lose-It behavior. • The RS8234 generates out-of-rate Forward RM cell(s) to restart • The RS8234 optionally posts the current Allowed Cell Rate (ACR) on the VBR Traffic Management The RS8234 schedules each VBR VCC according to GCRA parameters stored in the individual VCC control tables ...
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... The PCI interface between the host processor and the local system is controlled by Mindspeed’s Hardware Programming Interface (RS823xHPI), a software driver to the RS8234, on top of which a system designer can develop and place proprietary driver software. This interface allows users to easily port their applications to the RS8234. This software is written in C, and Source code is available under license agreement ...
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... High Performance Host Architecture with Buffer Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 2.2.1 Multiple ATM Clients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2.2 RS8234 Queue Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.2.3 Buffer Isolation Using Descriptor-Based Buffer Chaining . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.2.4 Status Queue Relation to Buffers and Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.2.5 Write-Only Control/Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2 ...
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... Segmentation VCCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2.1.1 Segmentation VCC Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2.1.2 VCC Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.2.2 Submitting Segmentation Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.2.2.1 User Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.2.2.2 Buffer Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.2.2.3 Host Linked Segmentation Buffer Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.2.2.4 Transmit Queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.2.2.5 Partial PDUs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.2.2.6 Virtual Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.2.3 CPCS-PDU Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 4.2.3.1 AAL5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 4.2.3.2 AAL3 4-9 8 ATM ServiceSAR Plus with xBR Traffic Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Mindspeed Technologies ™ RS8234 28234-DSH-001-B ...
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... RS8234 ATM ServiceSAR Plus with xBR Traffic Management 4.2.3.3 AAL0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 4.2.4 ATM Physical Layer Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 4.2.5 Status Reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 4 ...
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... Firewall Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29 5.4.11.1 Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29 5.4.11.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29 5.4.11.3 Credit Return . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31 5.5 Global Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31 Status Queue Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-32 5.6 5.6.1 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-32 5.6.1.1 Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33 5.6.1.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-34 5.6.1.3 Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-34 5.6.1.4 Host Detection of Status Queue Entries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35 5.6.2 Status Queue Overflow or Full Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35 Reassembly Control and Status Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-36 5.7 10 ATM ServiceSAR Plus with xBR Traffic Management Mindspeed Technologies ™ RS8234 28234-DSH-001-B ...
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... CBR Cell Delay Variation (CDV 6-13 6.2.3.4 CBR Channel Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15 6.2.4 VBR Traffic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16 6.2.4.1 Mapping RS8234 VBR Service Categories to TM 4.1 VBR Service Categories . . 6-16 6.2.4.2 Rate-Shaping vs. Policing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16 6.2.4.3 Single Leaky Bucket . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16 6 ...
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... Out-of-Rate Backward RM Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-35 GFC Flow Control Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-36 6.4 6.4.1 A Brief Overview of GFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-36 6.4.2 The RS8234’s Implementation of GFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-36 6.4.2.1 Configuring the Link for GFC Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-37 Traffic Management Control and Status Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-38 6.5 6 ...
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... RS8234 ATM ServiceSAR Plus with xBR Traffic Management 6.5.5.1 ABR Schedule State Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-45 6.5.6 ABR Instruction Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-48 6.5.7 RS_QUEUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-52 6 ...
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... System Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17 10.8 Real-Time Clock Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17 RS8234 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-18 10.9 11.0 PCI Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11 ...
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... Slave UTOPIA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8 12.7 Loopback Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10 12.8 Receive Cell Synchronization Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11 12.9 Transmit Cell Synchronization Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12 13.0 RS8234 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13.1 13.2 System Registers ...
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... ATM Physical Interface Timing—UTOPIA and Slave UTOPIA . . . . . . . . . . . . . . . . . . . . . . . 15-3 15.1.3 System Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6 15.1.4 RS8234 Memory Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8 15.1.5 PHY Interface Timing (Standalone Mode 15-12 15.1.6 Local Processor Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-14 15 ...
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... Multiple Client Architecture Supports Clients . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Figure 2-2. RS8234 Queue Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Figure 2-3. Interaction of Queues with RS8234 Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Figure 2-4. Reassembly Buffer Isolation — Data Buffers Separated from Descriptors . . . . . . . . . . . . . 2-6 Figure 2-5. Segmentation Buffer Isolation — Data Buffers Separated from Descriptors . . . . . . . . . . . . 2-7 Figure 2-6 ...
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... Local Processor Quad Write, No Wait States 10-10 Figure 10-7. i960CA/CF to the RS8234 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11 Figure 10-8. RS825x and SAR (RS8234) Interface (Standalone Operation 10-14 Figure 10-9. RS8234/PHY Functional Timing with Inserted Wait States . . . . . . . . . . . . . . . . . . . . . . . 10-15 Figure 10-10. RS8234/RS825x Read/Write Functional Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16 18 ATM ServiceSAR Plus with xBR Traffic Management Mindspeed Technologies ™ RS8234 28234-DSH-001-B ...
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... Synchronous PHY Interface Output Timing 15-13 Figure 15-11. Synchronous Local Processor Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-15 Figure 15-12. Synchronous Local Processor Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-15 Figure 15-13. Local Processor Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-17 Figure 15-14. Local Processor Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-18 Figure 15-15. 388-Pin Ball Grid Array Package (BGA 15-22 Figure 15-16. RS8234 Pinout Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-23 28234-DSH-001-B Mindspeed Technologies ™ List of Figures 19 ...
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... List of Figures 20 ATM ServiceSAR Plus with xBR Traffic Management Mindspeed Technologies ™ RS8234 28234-DSH-001-B ...
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... List of Tables Table 2-1. Hardware Signal Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29 Table 3-1. RS8234 Control and Status Queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 Table 3-2. Write-Only Control Queue Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 Table 3-3. Write-only Status Queue Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 Table 4-1 ...
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... ATM Service Category Parameters and Attributes 6-1 Table 6-2. Selection of Schedule Table Slot Size by System Requirements . . . . . . . . . . . . . . . . . . . . . . 6-7 Table 6-3. RS8234 VBR to TM 4.1 VBR Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16 Table 6-4. ABR Cell Type Decision Vector (ACDV 6-27 Table 6-5. Schedule Slot Entry — CBR/Tunnel Traffic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-38 Table 6-6. CBR_TUN_ID Field, Bit Definitions — ...
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... Table 12-2. UTOPIA Mode Signals 12-3 Table 12-3. Slave UTOPIA Mode Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3 Table 13-1. RS8234 Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 Table 14-1. Table of Values for Segmentation Control Register Initialization . . . . . . . . . . . . . . . . . . . . . 14-2 Table 14-2. Table of Values for Segmentation Internal Memory Initialization 14-3 Table 14-3 ...
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... List of Tables Table 15-6. SAR Shared Memory Output Loading Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8 Table 15-7. RS8234 Memory Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9 Table 15-8. PHY Interface Timing (PROCMODE = 15-12 Table 15-9. Synchronous Processor Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-14 Table 15-10 ...
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... Architecture Overview 2.1 Introduction The RS8234 ServiceSAR architecture efficiently handles high bandwidth throughput across the spectrum of three different ATM Adaptation Layers and all ATM service categories. This chapter provides an overview of this architecture. The first section describes the queue and data buffer system. Then, segmentation and reassembly functions are described from within the context of the queue structures ...
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... Multiple ATM Clients The RS8234, functioning as an ATM UNI, provides a high throughput uplink to a broadband network. Most individual ATM service users (or clients) do not have the bandwidth requirements to equal the throughput capability of the RS8234 application example, ATM clients may be Ethernet or Frame Relay ports ...
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... PCI Motherboard 2.2.2 RS8234 Queue Structure The flow of the reassembly, scheduling, and segmentation processes in the RS8234 is monitored, coordinated, and controlled through the use of a full array of circular queues, serviced by the RS8234 or by the host. The following queues exist in local memory: • Transmit queues ( queues) • ...
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... One of these may be designated as the Global OAM segmentation status queue. The host further processes these segmentation status queue entries. The RS8234 reports reassembly status to the reassembly status queues. One of these may be designated as the Global OAM reassembly status queue. The host further processes these reassembly status queue entries. ...
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... ATM ServiceSAR Plus with xBR Traffic Management These queues, placed on asynchronous communication paths, directly associate the host with the RS8234 during processing, and associate each of the major functional blocks of the RS8234 with each other. these interactions. The arrows indicate which system entity writes to each queue, and which entity reads each queue ...
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... High Performance Host Architecture with Buffer Isolation 2.2.3 Buffer Isolation Using Descriptor-Based Buffer Chaining The RS8234 employs buffer structures for reassembly and segmentation. The buffer structures maximize the flexibility of the system architecture by isolating the data buffers from the mechanisms that handle buffer allocation and linking. ...
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... RS8234 ATM ServiceSAR Plus with xBR Traffic Management Figure 2-5 the transmit queue for segmentation. The process is as follows Figure 2-5. Segmentation Buffer Isolation — Data Buffers Separated from Descriptors (Write) Host Memory Data Buffers LEGEND: Associations (Pointing Function) Data Reads ...
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... High Performance Host Architecture with Buffer Isolation 2.2.4 Status Queue Relation to Buffers and Descriptors The status queues employed by the RS8234 are written by the SAR and read by the host. These status queue entries provide the data needed by the host in order to further process the segmentation and reassembly data flow in progress or just completed ...
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... RS8234 ATM ServiceSAR Plus with xBR Traffic Management Figure 2-7 and reassembly data buffers and descriptors. The host submits free buffers to the SAR by writing pointers to them in the free buffer queue entries. The SAR links the buffer descriptors pointing to the three data buffers containing the reassembled PDU, and writes the RSM status queue entry containing the pointer to the first buffer descriptor for that PDU ...
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... PCI reads, the Bus Master retrieves the data from the slave while holding the bus. Since the data retrieval takes some time, reads increase the PCI bus utilization time for each transaction. The RS8234 eliminates read operations except for burst reads to gather segmentation data. ...
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... PDU boundaries (called Message Mode data buffer boundaries (called Streaming Mode). The RS8234 can also be configured with a status queue interrupt delay, which can be enabled in order to reduce the interrupt processing load on the host. This has value when the SAR resides in an environment in which the host is not dedicated to datacom processing ...
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... VCCs onto the line with cell level interleaving. For each cell transmission opportunity, the xBR Traffic Manager tells the segmentation coprocessor which VCC to send. The RS8234 provides full support of the AAL5 and AAL3/4 protocols and a transparent or NULL adaptation layer, AAL0. Each segmentation channel is specified as a single entry in the segmentation VCC Table located in SAR shared memory ...
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... The RS8234 provides a method to segment traffic from a fixed PCI address (or Virtual FIFO). This is intended for circuit-based CBR traffic such as voice channel(s). The RS8234 reports segmentation status to the host on one of a set of 32 independent parallel segmentation status queues. The RS8234 writes segmentation status queue entries on either PDU boundaries or buffer boundaries, selectable on a per-VCC basis ...
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... ATM ServiceSAR Plus with xBR Traffic Management Payload Type Identifier (PTI) termination, wherein the PTI bit in the cell header is monitored for the End of Message (EOM) cell indication Cell Count termination, wherein the RS8234 terminates the PDU when a user-defined number of cells have been received on that channel Mindspeed Technologies ™ ...
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... Per-VCC activation and control of a background hardware time-out • Per-VCC monitoring of the length of the reassembled PDU, with status The RS8234 implements an early packet discard feature to enable discarding of complete or partial CPCS-PDUs based upon service discard attributes or error conditions. The early packet discard function halts reassembly of the CPCS-PDU marked for discard until the next Beginning of Message (BOM) cell and/or the error condition has cleared ...
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... Advanced xBR Traffic Management The RS8234 implements ATM’s inherent robust traffic management capabilities for CBR, VBR, ABR, UBR, GFR and GFC. The RS8234 manages each VCC independently and dynamically. • The user assigns each connection a service class, a priority level, and a rate if • ...
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... Each conforming non-CBR VCC is assigned to a priority queue, while conforming CBR VCCs are simply slated for transmit. (5) The highest priority conforming cell is formatted and put on the Tx FIFO buffer for transmit. 28234-DSH-001-B The RS8234 asynchronously multiplexes traffic based on the above schemes, as the Tx FIFO empties. (2) SAR Segmentation ...
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... CDV. The RS8234 facilitates these needs when generating CBR traffic by pre-assigning specific schedule slots to CBR VCCs. For each CBR assigned cell slot, the RS8234 generates a cell for that specific VCC unless data is not available. The RS8234 also minimizes CDV by basing all traffic management on a local reference clock ...
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... The RS8234 injects an in-rate stream of Forward RM cells for each ABR VCC. When these cells return to the RS8234’s receive port as Backward RM cells after a round trip through the network, the RS8234 processes these cells and uses the data returned as feedback to dynamically adjust the rates on each ABR channel ...
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... The xBR Scheduler implements Mindspeed’s proprietary per-VCC rate shaping algorithms. The predecessor to the RS8234, the Bt8230 SAR, proved the core algorithms. The RS8234 extends their use to other service classes. The RS8234 xBR Scheduler shapes all traffic classes, including CBR, single leaky bucket VBR, dual leaky bucket VBR, ABR, and UBR ...
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... ABR Flow Control Manager The ABR Flow Control Manager operates in conjunction with the xBR Scheduler to control the rate of ABR channels. The RS8234 implements the TM 4.1 specification in a template-controlled hardware state machine. Mindspeed provides an initial set of templates which reside in SAR shared memory. The information within these templates define conformant ABR behavioral responses to network and connection states ...
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... Burst FIFO Buffers To conserve local memory bandwidth, the RS8234 does not use its local SRAM as a buffer for incoming or outgoing data. Instead, the RS8234 uses six dedicated internal FIFO data buffers as follows: • Two DMA master burst FIFO buffers (read =16 words; write=512 words. ...
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... RS8234 provides the option of user-defined global status queues for both segmentation and reassembly and a global buffer queue for reassembly, to which the user can assign SAR shared memory addresses. The RS8234 will then process OAM traffic via the local processor, thereby isolating the host from these management functions and focusing host processing power on ATM user data traffic ...
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... To simplify system implementations, the RS8234 integrates a complete memory controller designed for direct interface to common Static RAMs (SRAMs). The RS8234’s memory controller operates at 33 MHz and can access SRAM memory. The memory controller also arbitrates access to the internal control and status registers by the host and local processors. The memory banks can be configured to a variable number of sizes ...
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... Electrical/Mechanical The RS8234 is a CMOS device packaged in a 388 Ball Gate Array (BGA) format. It operates from a 3.3V power supply and within the standard industrial temperature range. The device inputs are tolerant signal levels, so external 5 V devices may be used ...
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... Architecture Overview 2.10 Logic Diagram and Pin Descriptions Figure 2-11. RS8234 Logic Diagram ( Address/Data Bus I/O Command/Byte Enable I/O Address/Data Command Parity I/O Framing Signal I/O Transactor Initiator Ready I/O Transaction Target Ready I/O Transaction Termination I/O Bus Device Acknowledge I/O Bus Device Slot Select I Bus Grant I Bus Parity Error ...
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... RS8234 ATM ServiceSAR Plus with xBR Traffic Management RS8234 Logic Diagram ( AF12 Framer Configuration I AE12 Framer Configuration I AF15 Transmit Cell Marker I/O AF16 Transmit Flag I/O Transmit Enable I/O AC14 AE7 Receive Data I AF7 AC8 AD8 AE8 AF8 AC9 AF9 Receive Data Parity ...
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... Architecture Overview 2.10 Logic Diagram and Pin Descriptions RS8234 Logic Diagram ( Memory Data Bus I AA1 AA3 AA4 AB1 AB2 AB4 AC1 AC2 AC3 B9 Memory Address Bus I ...
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... I/O Used by the transaction initiator or bus master (either the RS8234 or the PCI host) to indicate ready for data transfer. A valid data phase ends when both HIRDY* and HTRDY* are sampled asserted on the same clock edge. I/O ...
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... Signals an interrupt request to the PCI host, and is tied to the INTA_ line on the PCI bus. I/O Driven asserted by the RS8234 (as a bus slave target addressed by the RS8234 when it acts as a bus master to indicate a parity error on the HAD[31:0] and HC/BE[3:0]* lines asserted when the RS8234 is a bus slave or sampled when the RS8234 is a bus master on the second clock edge after a valid data phase ...
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... RxData[7:0], RxPar, and RxSOC lines are invalid. In slave UTOPIA mode, this pin indicates to the framer chip that the receive FIFO buffer in the RS8234 is full drive. Has pulldown resistor to pull inactive in master mode when not driven externally. (aka RxFlag*) ...
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... The PADDR[1,0] inputs are connected to the word select field of the CPU address bus (address bits [3, 2] for the Intel i80960CA processor, which can perform 4-word burst transactions). These inputs are used by the RS8234 to allow single-cycle bursts to be performed without requiring very short memory access times. ...
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... The local processor can indicate a failure of its internal self-test or initialization processes by asserting the PFAIL* input to the RS8234. OD Asserted by the RS8234 to the local processor to signal an interrupt request in local processor mode. O Asserted by the RS8234 to the local processor whenever the HRST* input is asserted, or when the LP_ENABLE bit in the CONFIG0 register is a logic low ...
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... Provides Electrostatic Discharge (ESD) protection and over voltage protection. When the device is used with 5 V devices on the board, tie this pin for 5 V signal tolerance. Otherwise, tie to 3.3 V. The 5 V supply must be applied concurrent to the 3.3 NOTE: V supply. Mindspeed Technologies ™ RS8234 Definition 28234-DSH-001-B ...
Page 67
... RS8234’s high throughput, the host must process control and status information at a comparable rate. An Ethernet Switch uses a RS8234 based subsystem as an uplink to an OC-3 ATM backbone. Under worst case conditions, Ethernet packets (64 octets) map into two ATM cells. At OC-3 rates, the RS8234 converts 176.6 k packets/second to cells in each direction ...
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... The host assigns each of these independent flows to system clients, or peers. As throughput requirements escalate, the host system can add processing power in the form of additional peers. This degree of freedom creates a scalable host environment. The RS8234 provides an ATM server for clients. client/server relationship. ...
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... Frame Relay adapter cards experiences a hardware failure. The failure prevents the card’s processor from servicing the RS8234’s reassembly status queue. Eventually, the RS8234 fills the queue and is unable to proceed — this situa- tion is referred to as queue overflow. The RS8234 shuts down reassembly on VCCs that are assigned to the overflowed queue only ...
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... Peer-to-Peer Transfers The multiple queue architecture of the RS8234 also enables peer-to-peer PCI transfers. The RS8234 transfers ATM cells as a PCI master. Since the buffer control structures are independent for each peer, each identifies a unique address range in PCI memory space. The host defines the address range of each peer. The RS8234 transfers data within this address range ...
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... ATM ServiceSAR Plus with xBR Traffic Management 3.2.5 Local Processor Clients The RS8234 supports limited bandwidth SAR shared memory segmentation and reassembly. Any peer may use the local processor port instead of the PCI bus for control and status, as well as for data traffic. Hosts can use SAR shared memory for control and status, but transfer data across the PCI bus. This “ ...
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... These queues reside in SAR shared memory at a location defined by a base register pointer. To allow multiple clients, the RS8234 supports 32 queues of each type. The SAR and host manage each queue independently, through queue management variables. The SAR stores its variables in internal registers called base tables ...
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... RS8234 ATM ServiceSAR Plus with xBR Traffic Management 3.3.1.1 Control Table 3-2 Variables Table 3-2. Write-Only Control Queue Variables Variable WRITE Current host position in queue READ_UD Last known SAR position in queue as seen by host READ Current SAR position in queue INTERVAL Number of queue entries processed by SAR ...
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... The RS8234 “snoops” writes to the control queue areas. Once a write is detected to a specific queue, the SAR attempts to process the queue entry at READ. Before acting on the entry, the SAR checks for ownership of the entry, indicated by the VLD bit. Once the RS8234 has processed the entry, it resets the VLD bit to zero. 3.3.1.3 Underflow ...
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... The host must assign word aligned (4-byte) status queue base addresses. To support multiple clients, the RS8234 provides 32 queues of each type. The SAR and host manage each queue independently through queue management variables. The SAR stores its variables in internal base table registers ...
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... Management all of the variables described in The SAR maintains its own write pointer, WRITE. The RS8234 reports status to the host by writing a status queue entry. After it writes the entry, the RS8234 increments its write pointer (WRITE++). This write also triggers a maskable interrupt. The host either responds to this interrupt, or periodically polls the status queue ...
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... READ_UD -1), the SAR detects the imminent overflow condition. To inform the host of the event, the SAR sets the overflow indication bit (OVFL) in the exhausted status queue. Since it cannot report status, the RS8234 segmentation and reassembly processing is temporarily halted for VCCs assigned to the overflowed status queue only. All other processes and queues remain operational ...
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... STAT_CNT, the interrupt window will be opened, which will allow the interrupt to propagate to the output pin. The counter is reset when the status registers are read and the interrupt output goes inactive. 3-12 ATM ServiceSAR Plus with xBR Traffic Management Mindspeed Technologies ™ RS8234 28234-DSH-001-B ...
Page 79
... In addition to converting blocked user data into ATM cells, the RS8234 generates all AAL overhead for AAL3/4 and AAL5, or optionally uses a null adaptation layer, AAL0. The RS8234 also generates the ATM cell header, as defined by the host, for each VCC. Furthermore, the segmentation coprocessor and xBR Traffic Manager together provide service specific features to enhance the performance of Frame Relay internetworking and LAN Emulation ...
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... Segmentation Functional Description 4.2 Segmentation Functional Description 4.2.1 Segmentation VCCs A VCC specifies a single the ATM network. The RS8234 supports segmentation VCCs, referenced by a unique index, VCC_INDEX. The VCC_INDEX identifies a location in the Segmentation VCC Table, an array of 10-word segmentation VCC channel descriptors. ...
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... RS8234 ATM ServiceSAR Plus with xBR Traffic Management Figure 4-1. Segmentation VCC Table Base Register (SEG_VBASE(SEG_VCCB)<<5) VCC_INDEX = 0x3 VCC_INDEX = 0x1000 (ABR VCC) VCC_INDEX = 0xFFFD (non-ABR VCC) The VCC Table entry contains generic information common to all traffic classes. This includes a default ATM header, which the host may modify during the segmentation process ...
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... VCCs. The SAR accepts PDUs at any time, regardless of the state of the connection, and segments data on each VCC independently. 4.2.2.1 User Data The RS8234 accepts user PDUs as sequences of data buffers. SAR shared Format memory resident segmentation buffer descriptors (SBDs) provide the address, length and control information for buffers. The host forms PDU buffer sequences by linking buffer descriptors ...
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... The RS8234 detects this write by “snooping” SAR shared memory accesses. When a write occurs to any of the transmit queues, the RS8234 marks that queue as pending. Once every cell slot, the RS8234 services one queue entry from one Transmit Queue. The system designer selects one of two service order priority schemes ...
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... The SAR will link the new SBDs to the current chain of SBDs on a VCC. The host can submit data to a VCC while the SAR is segmenting a previously submitted message. Once the chain has been linked, the RS8234 resets the transmit queue VLD bit to zero. ...
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... Partial PDUs The host may submit partial PDUs to the RS8234. In this case, the SAR transmits the data and halts on a cell boundary. The partial PDU buffers are not required to be aligned to a cell boundary by the host. The RS8234 tracks the remaining segmentation data ...
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... AAL_MODE = AAL5 (b00), and AAL_OPT = ABORT (b01). Figure 4-5 internal circuits to generate and store PDU length and CRC-32 in the SEG VCC Table. The RS8234 transmits these fields within the EOM cell. The PAD and CPI fields are generated internally. Figure 4-5. AAL5 CPCS-PDU Generation ...
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... ATM ServiceSAR Plus with xBR Traffic Management 4.2.3.2 AAL3/4 When a segmentation buffer descriptor’s AAL_MODE field is set to AAL3/4 (value = b10), the RS8234 generates the CPCS-PDU’s CPI, Btag, Etag, BASize, Alignment (AL), and Length fields in the header and trailer of the CPCS-PDU, and pads the PDU to align to a cell boundary. ...
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... CRC-10 generator before transmission by setting the CRC_10 option in the seg buffer descriptor. shows the settings for the ST (Segment Type) field. Segment Type Encoding BOM 10 COM 00 EOM 01 SSM 11 Mindspeed Technologies RS8234 Table 4-3. Function Usage Beginning of Message Continuation of Message End of Message Single Segment Message ™ 28234-DSH-001-B ...
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... Etag = Ending Tag (see Btag above). 6. Length = Contains the exact size of the PDU's payload. 4.2.3.3 AAL0 The RS8234 also supports a transparent or NULL adaptation layer, AAL0. AAL0 maps CPCS-SDUs directly to CPCS-PDU payloads. The SAR pads the SDU to a 48-byte cell payload boundary, but generates no other overhead. The SAR generates the ATM header and PDU termination indications in the same manner as it does with AAL5 ...
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... VCC_INDEX of the VCC on which the buffer was transmitted. 4.2.6 Virtual FIFOs In addition to gathering PDU data from buffers, the RS8234 provides an optional method to segment from a fixed PCI address, or Virtual FIFO. The RS8234 supports AAL0, CBR Virtual FIFO segmentation. The host configures the channel for Virtual FIFO operation by setting the CURR_PNTR and RUN fields to zero in the SEG VCC Table entry ...
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... RS8234 ATM ServiceSAR Plus with xBR Traffic Management 4.3 Segmentation Control and Data Structures 4.3.1 Segmentation VCC Table Entry Each Segmentation VCC Table entry occupies one 10-word descriptor of the Segmentation VCC Table. The first seven words are generic, independent of traffic class. The last words provide additional parameters specific to service classes ...
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... This word is used for AAL5 and AAL0 VCCs. (2) This word is used for AAL3/4 VCCs. 4-14 ATM ServiceSAR Plus with xBR Traffic Management = Written by host at VCC setup = May be dynamically modified during active segmentation LAST_PNTR Rsvd ATM_HEADER CRC_REM BETAG Rsvd SN CURR_PNTR SCH_STATE Mindspeed Technologies ™ RS8234 BOM_PNTR BUFFER_LEN MID NEXT_VCC 28234-DSH-001-B ...
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... The address of the buffer descriptor is (LAST_PNTR << (LAST_PNTR * 4). UU AAL5 User-to-User indication. This field is copied from the buffer descriptor UU field. The RS8234 inserts the UU field in the CPCS-PDU trailer contained in the EOM cell. BOM_PNTR In Message mode (STM_MODE=0), points to the first buffer descriptor of a message composed of more than one buffer descriptor ...
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... Specific scheduling state information. The contents of this field depend on the setting of the SCH_MODE field not used when SCH_MODE is set to UBR. (The contents of this field are detailed in Chapter NEXT_VCC Used by SAR to link VCCs in schedule chains. 4-16 ATM ServiceSAR Plus with xBR Traffic Management Description Chapter 6.0 for details.) 6.0.) Mindspeed Technologies ™ RS8234 28234-DSH-001-B ...
Page 95
... RS8234 ATM ServiceSAR Plus with xBR Traffic Management Table 4-7 setup values for restricted fields. the AAL3/4-AAL5-AAL0 format. Table 4-7. Segmentation VCC Table Entry — Virtual FIFOs Word ...
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... Data Buffers Data buffers contain CPCS-SDUs for segmentation and reside in host or SAR shared memory. The RS8234 retrieves host data buffers from any byte aligned PCI address using the “READ Multiple” PCI command. SAR shared data buffers must be aligned on word boundaries. Buffers contain any number of bytes of only user data maximum ...
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... BUFFER_PNTR is a byte aligned PCI address BUFFER_PNTR is a word aligned address in SAR shared memory instead of host memory. SET_CI 0 - The RS8234 generates bit 1 of PTI[2:0] from the VCC Table Entry ATM_HEADER field Sets bit 1 of the ATM header PTI[2:0] field for all cells in buffer to one. SET_CLP 0 - The RS8234 generates the CLP bit from the VCC Table Entry ATM_HEADER field ...
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... The RS8234 generates the VCI field from the VCC Table Entry ATM_HEADER field The RS8234 generates the VCI field from the NEW_VCI for all cells in the buffer. NEW_VCI will also be copied in to the VCI portion of the ATM_HEADER field in the VCC entry. ...
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... Data for the RPL_VCI. The RS8234 overwrites the VCC Table Entry ATM_HEADER VCI field with this data. Therefore, the effect is permanent until the next buffer descriptor with RPL_VCI is processed. SEG_VCC_INDEX Identifies the VCC Entry in the VCC Table. The RS8234 links this buffer descriptor to the identified VCC. 4.3.4 Transmit Queues 4.3.4.1 Entry Format The host submits chains of SBDs to the RS8234 by writing a single word transmit queue entry ...
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... Field Name LINK_HEAD 0 - The RS8234 links the new descriptor chain at the end of the existing chain on the VCC The RS8234 links the new descriptor chain at the head of the existing chain. If this bit is set, the buffer must contain data for at least one cell. Only a single buffer descriptor may be linked to a transmit queue entry when this bit is set ...
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... READ SAR read pointer. Represents the SAR’s current position in the transmit queue. 4.3.5 Segmentation Status Queues 4.3.5.1 Entry Format The RS8234 reports segmentation to the host status queues. Each entry on the queue is two words. entries. Table 4-18. Segmentation Status Queue Entry Word ...
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... Although the SAR handles this condition, the host should attempt to prevent overflows. The RS8234 detects when it writes the last available entry in a status queue (WRITE=READ_UD-1), and alerts the host to this condition by setting the OVFL bit in the status entry. Until the host services the queue and increments the READ_UD pointer in the base table register, the RS8234 inhibits segmentation on all channels that report on the overflowed status queue ...
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... RS8234 ATM ServiceSAR Plus with xBR Traffic Management 4.3.6 Segmentation Internal SRAM Memory Map As indicated in range 0x1400-0x17FF. The segmentation status queue base table registers (SEG_ST_QUn) are in the address range 0x1400-0x14FF. The internal transmit queue base table registers (SEG_TQ_QUn) are in the address range 0x1500-0x15FF. ...
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... Segmentation Coprocessor 4.3 Segmentation Control and Data Structures 4-26 ATM ServiceSAR Plus with xBR Traffic Management Mindspeed Technologies ™ RS8234 28234-DSH-001-B ...
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... Physical Interface block. The coprocessor extracts the AAL SDU payload from the received cell stream and reassembles this information into buffers supplied by the host system. The RS8234 supports AAL5, AAL3/4, and AAL0 reassembly, as well as cell mode (1-cell PDUs through a Virtual FIFO, for CBR voice traffic). ...
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... VCC, thereby demultiplexing the incoming messages. Figure 5-1 Figure 5-1. Reassembly—Basic Process Flow ATM Cells ATM Network 5-2 ATM ServiceSAR Plus with xBR Traffic Management illustrates the basic reassembly process flow. Messages Reassembly Coprocessor Mindspeed Technologies ™ RS8234 Host (64 K) 100074_022 28234-DSH-001-B ...
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... VC. Each VC may be processed as either AAL5, AAL3/4, or AAL0. AAL0 VCs can optionally be treated as Virtual FIFOs. While the RS8234 will accept any reassembly VCC Index within the range VCC Indexes, the actual number of reassembly VCCs allowed by the SAR is limited by the amount of SAR shared memory available in which to allocate and create RSM VCC Tables, free buffer queues, RSM status queues, etc ...
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... Reassembly Coprocessor 5.2 Reassembly Functional Description 5.2.2 Channel Lookup The RS8234’s reassembly coprocessor implements a VPI/VCI Index Table mechanism using direct index lookup in order to assign each cell to a virtual channel, based on its VPI/VCI value. Each channel is thus identified by its internally generated index value, the VCC_INDEX. ...
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... Programmable Some users might have a requirement or desire to limit the amount of memory Block Size for VCC Table/ allocated to VPI/VCI channel lookup. To enable this, the RS8234 provides the VCI Index Table user with the choice of enabling an alternative scheme for the memory allocation and table handling involved in the Direct Index Lookup mechanism. In this scheme, the user programs the size of the memory block of RSM VCC Table entries for all VCI Index table entries, to fit a range of 1– ...
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... CELL_DSC_CNT counter. The VCI_IT_PNTR indicates the base address of the VPI’s VCI Index table. The RS8234 then reads the appropriate entry in the VCI Index table. The address of the VCI Index Table entry is derived as follows: The VCC_BLOCK_INDEX in the VCI Index table entry selects a contiguous block of 64 reassembly VCC State Table entries (or from 1– ...
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... Optionally, the counter is not incremented if the AAL_TYPE field has a value of ‘11’. VC_EN allows idle cells to be filtered if the PHY layer has not already done so. If the channel is active, the RS8234 increments the CELL_RCVD_CNT counter. 5.2.2.4 AAL3/4 Lookup AAL3/4 MID multiplexing requires an additional level of indirection in channel lookup for received AAL3/4 traffic ...
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... OPERATION Once the reassembly process is activated, this RSM VCC table entry will be used to track the current state of the connection and direct the RS8234 to perform specific functions as described throughout this chapter. 5-8 ATM ServiceSAR Plus with xBR Traffic Management illustrates the basic process function ...
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... RS8234 ATM ServiceSAR Plus with xBR Traffic Management 5.3.1 AAL5 Processing Except for the EOM cell, all of the data within AAL5 cell payloads is user data. The reassembly coprocessor writes all user data to memory as described in Section delineates the end of an AAL5 PDU. 5.3.1.1 AAL5 COM ...
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... Data) CRC-32 Length Accumulator Counter The RS8234 reports all PDU termination events, with or without errors status queue entry for that channel. See 5-10 ATM ServiceSAR Plus with xBR Traffic Management bit in the status queue entry is set to a logic high. trailer of the AAL5 PDU. If different, the reassembly coprocessor sets the CRC_ERROR bit in the status queue entry to a logic high ...
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... SDU delivery length. If the RS8234 receives a non-EOM cell, where Early Packet Discard is performed. The RS8234 reports this condition via a status queue entry, with the LEN_ERROR and EPD status bits set. The AAL5_DSC_CNT counter is also incremented. Refer to For each EOM cell where the PDU is completed, with BA_ERROR status bit set ...
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... CRC = A CRC check of the 48-byte ATM cell payload. 5-12 ATM ServiceSAR Plus with xBR Traffic Management illustrates an AAL3/4 CPCS-PDU reassembled from the received <64 K Payload MID LI CRC Mindspeed Technologies ™ RS8234 Section 5.4. The EOM PAD AL Etag Length Trailer MID PAD LI CRC 100074_030 ...
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... RS8234 ATM ServiceSAR Plus with xBR Traffic Management 5.3.2.1 AAL3/4 Per-Cell The following processing steps and checks occur on a per-cell basis: Processing • If the CRC10_EN bit in the AAL3/4 Head VCC table entry is a logic high, • The MID field value is checked against active MID values specified by the • ...
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... When a BOM cell is received for an AAL3/4 CPCS-PDU (i.e., with ST • The RS8234 also checks if the BAH_EN bit in the RSM AAL3/4 Head • If the CPI and BASIZE fields are correct in the BOM cell, the RS8234 • If the LI field in the SAR-PDU > (BASIZE+7), the SAR discards the cell, 5 ...
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... Processing • The Length field in the CPCS-PDU trailer is written to the • The RS8234 performs a Pad length check to see if the sum of all LIs for • The RS8234 performs a Modulo 32 bit check. If the sum of all LIs for the • If the Alignment (AL) field in the CPCS-PDU trailer is not all zeros, it sets • ...
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... PTI[0]= AALO PDU The RS8234 reports all PDU termination events, with or without errors Status Queue entry for that channel. See 5.3.3.2 AAL0 Error If the RS8234 receives a non-EOM cell in PTI termination mode, where Conditions EPD is performed. The RS8234 reports this condition via a status queue entry, with the LEN_ERROR and EPD status bits set ...
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... RS8234 ATM ServiceSAR Plus with xBR Traffic Management 5.3.5 BOM Synchronization Signal The STAT[1:0] output pins can be programmed to provide an indication that a BOM cell is being written across the PCI bus. Additional external circuitry could snoop the BOM cell for a service level protocol header, and perform appropriate lookup as the CPCS-PDU is being reassembled ...
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... PCI bus being held in a busy state while the remote processor accesses and processes the read request. Therefore, to speed up processing flow during reassembly, the RS8234 uses only control and status writes across the PCI bus between host and local systems ...
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... RS8234 ATM ServiceSAR Plus with xBR Traffic Management 5.4.2 Scatter Method The RS8234 uses an intelligent scatter method to write cell payload data to host memory. During reassembly to host memory, the reassembly coprocessor uses the DMA coprocessor to control the scatter function. The reassembly coprocessor controls the incoming DMA block during scatter DMA to host memory. ...
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... ATM ServiceSAR Plus with xBR Traffic Management FBQx_BASE + [(size of each free buffer queue) x BFRx MOD 16] (index of first entry for the queue) + [(READ index pointer) x (size of each free buffer queue entry)] Mindspeed Technologies ™ RS8234 28234-DSH-001-B ...
Page 125
... RS8234 ATM ServiceSAR Plus with xBR Traffic Management Figure 5-12 information on the operation of the Free Buffer Queue. Figure 5-12. Free Buffer Queue Structure FBQ Base Table (Internal SRAM) RSM_FBQ_QU0 0x1100 BFRx (BFR0 or BFR1) READ 28234-DSH-001-B illustrates this structure. Refer to Free Buffer Queue Bank ...
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... Only the data buffers are affected by big/little endian processing. The buffer control structures (i.e., the buffer descriptors, free buffer queue base table, and free buffer queues) are the same in both big and little endian modes. Mindspeed Technologies ™ RS8234 Buffers (Host Memory) 100074_034 28234-DSH-001-B ...
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... Initialize the free buffer queue update INTERVAL, i.e., how many buffers are taken off the free buffer queue before the RS8234 writes the current READ index pointer to host memory. This is written to RSM_FQCTRL(FBQ_UD_INT). Initialize the FORWARD, READ, UPDATE, and EMPT fields in each free buffer queue base table entry to zeroes ...
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... UPDATE counter is reset to zero. When the host wants to return a buffer to a free buffer queue, the host WRITE index pointer is compared to the RS8234 READ index pointer located at READ_UD_PNTR. If the WRITE index pointer + one is equal to the READ index pointer, an overflow condition has been detected and further processing is halted ...
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... RS8234 ATM ServiceSAR Plus with xBR Traffic Management 5.4.8 Early Packet Discard The packet discard feature provides a mechanism to discard complete or partial CPCS-PDUs, based upon service discard attributes or error conditions. 5.4.8.1 General The EPD feature performs these basic functions: Description • Halts reassembly of the CPCS-PDU marked for discard until the next • ...
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... RSM status queue entry being a logic high. 5-26 ATM ServiceSAR Plus with xBR Traffic Management entry for this channel will be set to a logic high. The CNT_ROVR bit in the VCC Table holds this flag information until a status is sent. Mindspeed Technologies ™ RS8234 28234-DSH-001-B ...
Page 131
... TO_VCC_INDEX = RSM_TO_CNT, then TO_VCC_INDEX is reset to zero and the time-out search is restarted at the beginning of the VCC Tables. If both bits are set, the RS8234 increments CUR_TOCNT in the RSM VCC Table entry. Then it compares CUR_TOCNT to the time-out value selected, TERM_TOCNTx, where x = TO_INDEX. TERM_TOCNT0 through TERM_TOCNT7 are located at address 0x1340 through 0x134c in internal SRAM ...
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... When time-out processing is halted, the time-out process will still be activated, but the VCC will not be checked for a time-out condition. The RS8234 will simply increment TO_VCC_INDEX and compare it to RSM_TO_CNT. If they are equal, TO_VCC_INDEX is reset to zero and the full time-out processing is re-enabled ...
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... If the RX_COUNTER[15:0] for a channel is 0 when a buffer is required, the RSM coprocessor declares a firewall condition. If the firewall condition occurs on a BOM or SSM, the RS8234 writes a status queue entry with the FW bit set and a NULL in the BD_PNTR field. If the firewall condition occurs on a COM or EOM, the RSM coprocessor initiates EPD and writes a status queue entry with the FW and EPD bits set ...
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... Reassembly Coprocessor 5.4 Buffer Management All AAL5 PDU’s discarded under the firewall condition cause the AAL5_DSC_CNT counter to be incremented. Recovery occurs only on a BOM or SSM cell when the credit is rechecked. 5-30 ATM ServiceSAR Plus with xBR Traffic Management Mindspeed Technologies ™ RS8234 28234-DSH-001-B ...
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... When a write completes, the RS8234 will begin processing firewall return credits on that queue. The third word of each entry will be read, and if FWD_VLD is set, a credit will be added to the VCC_INDEX indicated. The RS8234 will continue to process credit return entries until FWD_VLD is zero. Multiple free buffer queues might have credit return entries outstanding at one time ...
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... Reassembly Coprocessor 5.6 Status Queue Operation 5.6 Status Queue Operation The RS8234 reports reassembly status to the host via the reassembly status queue. The reassembly coprocessor normally writes a status queue entry when a complete CPCS-PDU has been reassembled. One field of the status queue entry (BD_PNTR) points to the first buffer descriptor in the linked list of buffer ...
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... RS8234 ATM ServiceSAR Plus with xBR Traffic Management Figure 5-15 Figure 5-15. Status Queue Structure Format Status Queue Base Table (Internal SRAM) 0x1000 STAT (From RSM VCC BASE_PNTR Table Entry) WRITE (32 entries in the base table) 5.6.1.1 Setup At system initialization, set up the following fields in each of the status queue base table entries: • ...
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... RSM_LF_EMPT bit in the LP_ISTAT1 register is set to a logic high. This status does not point to a linked list of buffer descriptors. It will be written a maximum of once per free buffer queue empty condition. 5-34 ATM ServiceSAR Plus with xBR Traffic Management Chapter 2.0 for more detailed information on the operation of status Mindspeed Technologies ™ RS8234 28234-DSH-001-B ...
Page 139
... RS8234 ATM ServiceSAR Plus with xBR Traffic Management 5.6.1.4 Host Detection The host can use either a polling operation or an interrupt routine to detect new of Status Queue Entries status queue entries. To poll each status queue, the host continuously reads the VLD bit at the current READ position until it returns a logic high. The host then processes the status entry, writes the VLD bit to a logic low and increments its current READ pointer ...
Page 140
... VPI Index Table format (one word per entry) describes the VPI Index Table format (two words per entry) with describes the field definitions for the VPI Index Table fields. Mindspeed Technologies ™ RS8234 VCI Index Table (For One VPI) VCC_BLOCK_INDEX 100074_037 ...
Page 141
... RS8234 ATM ServiceSAR Plus with xBR Traffic Management Table 5-4. VPI Index Table Entry Format with EN_PROG_BLK_SX(RSM_CTRL1) Enabled Word Reserved Reserved 1 Table 5-5. VPI Index Table Entry Descriptions ...
Page 142
... AAL3/4-specific reassembly process state for an AAL3/4 VCC. Figure 5-17 continuation from Figure 5-17. Reassembly VCC Table Entry Lookup Mechanism Base Register RSM_TBASE(RSM_VCCB) VCC_BLOCK_INDEX 5-38 ATM ServiceSAR Plus with xBR Traffic Management Description/Function illustrates the VCC Table entry lookup mechanism as a Figure 5-16. VCI[5:0] Mindspeed Technologies ™ RS8234 100074_038 28234-DSH-001-B ...
Page 143
... RS8234 ATM ServiceSAR Plus with xBR Traffic Management 5.7.2.1 AAL5, AAL0, Table 5-9 and AAL3/4 VCC Table Table 5-10 Entries describes the format of AAL3/4 RSM VCC Table entries. KEY: Table 5-9. Reassembly VCC Table Entry Format - AAL5 Word ...
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... ATM ServiceSAR Plus with xBR Traffic Management Reserved PM_INDEX Reserved Reserved STAT CBUFF_PNTR BOM_BD_PNTR CURR_BD_PNTR Reserved Reserved PM_INDEX Reserved Reserved Rsvd STAT CBUFF_PNTR BOM_BD_PNTR CURR_BD_PNTR Mindspeed Technologies RS8234 AAL_EN ABR_CTRL TOT_PDU_LEN TCOUNT BFR1 BFR0 SERV_DIS RX_COUNTER/VPC_INDEX AAL_EN ABR_CTRL TOT_PDU_LEN NEXT_SN BTAG BFR1 BFR0 SERV_DIS RX_COUNTER/VPC_INDEX Reserved Reserved ™ ...
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... RS8234 ATM ServiceSAR Plus with xBR Traffic Management Table 5-12 illustrates the ABR_CTRL field bit definitions. AAL_EN field bit definitions. Table 5-12. PDU_FLAGS Field Bit Definitions Bit CNT_ROVR SFPD_PND EPD Table 5-13. ABR_CTRL Field Bit Definitions Bit 7 6 ER_EN Reserved Table 5-14. AAL_EN Field Bit Definitions ...
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... FRD_EN—Enable frame relay DE (Discard Eligibility) mode. Invalid in AAL3/4. CLPD_EN—Enable CLP discard mode. Invalid in AAL3/4. 5-42 ATM ServiceSAR Plus with xBR Traffic Management details the descriptions of the reassembly VCC Table fields. Description/Function LNK_EN FW_EN M52_EN BINTR Mindspeed Technologies ™ RS8234 STM_MODE LECID_EN FRD_EN CLPD_EN 28234-DSH-001-B ...
Page 147
... RS8234 ATM ServiceSAR Plus with xBR Traffic Management Table 5-15. Reassembly VCC Table Descriptions ( Field Name PDU_FLAGS Set various flags related to PDUs. The PDU_FLAGS field contains the following control bits: 31 CNT_ROVR CNT_ROVR—Indication that SERVICE_CNT counters have rolled over. The next status entry will indicate this condition. SFPD_PND— ...
Page 148
... RX_COUNTER/ When ABR_VPC is a logic low, RX_COUNTER is the firewall mode credit counter. When ABR_VPC is VPC_INDEX a logic high, VPC_INDEX is used to control a VPC group. See ABR_VPC for description of this field. 5-44 ATM ServiceSAR Plus with xBR Traffic Management Description/Function Mindspeed Technologies ™ RS8234 28234-DSH-001-B ...
Page 149
... RS8234 ATM ServiceSAR Plus with xBR Traffic Management 5.7.2.2 AAL3/4 Head Table 5-16 VCC Table Entry AAL3/4 Head VCC Table field definitions. Table 5-16. AAL3/4 Head VCC Table Entry Format Word ...
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... ATM ServiceSAR Plus with xBR Traffic Management Description/Function MID_BITS Range of MID values 0000 MID processing disabled 0001 0 / 1-1 0010 0 / 1-3 0011 0 / 1-7 0100 0 / 1-15 0101 0 / 1-31 0110 0 / 1-63 0111 0 / 1-127 1000 0 / 1-255 1001 0 / 1-511 1010 0 / 1-1023 1011 Reserved 1100 Reserved 1101 Reserved 1110 Reserved 1111 Reserved Mindspeed Technologies ™ RS8234 28234-DSH-001-B ...
Page 151
... RS8234 ATM ServiceSAR Plus with xBR Traffic Management Table 5-17. AAL3/4 Head VCC Table Descriptions ( Field Name TO_EN Enable time-out process of the VCC entry. Must be set to a logic zero. CRC10_ERR Number of AAL3/4 cells received with CRC10 error. MID_ERR Number of AAL3/4 cells received that did not have an active MID as determined by the MID_BITS and MID0 fields ...
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... The host initializes the free buffer queues in SAR shared memory, and during reassembly processing submits data buffers for reassembly to the free buffer queues. The free buffer queue base table is located in RS8234 internal memory. Table 5-20 entries. Table 5-20. Free Buffer Queue Base Table Entry Format ...
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... RS8234 ATM ServiceSAR Plus with xBR Traffic Management Table 5-22 Table 5-22. Free Buffer Queue Entry Format Word (1) Reserved 2 (1) 3 NOTE(S): (1) These words are used only in Bank 0 if RSM_FBQCTL(FBQ0_RTN ...
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... Reassembly Coprocessor 5.7 Reassembly Control and Status Structures 5.7.5 Reassembly Status Queues The RS8234 reports reassembly status to the host on any one of 32 reassembly status queues. At initialization the host assigns the location and size RSM status queues by initializing the reassembly status queue base table entries in RS8234 internal memory ...
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... RS8234 ATM ServiceSAR Plus with xBR Traffic Management Table 5-27. Reassembly Status Queue Entry Format with FWD_PM = 1 Word TRCC0 2 Rsvd PDU_CHECKS 3 Reserved Table 5-28. Reassembly Status Queue Entry Format with FWD_PM = 0 and AAL34 = 1 ...
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... Indication that the status entry is relative to an AAL3/4 PDU. Also indicates that HEAD_VCC_INDEX and A3L2_ERR fields are active. This field is only active when FWD_PM = 0. NOTE: 5-52 ATM ServiceSAR Plus with xBR Traffic Management Description/Function AAL3/4: BASIZE field error occurred. Mindspeed Technologies ™ RS8234 28234-DSH-001-B ...
Page 157
... RS8234 ATM ServiceSAR Plus with xBR Traffic Management Table 5-33. Reassembly Status Queue Entry Descriptions ( Field Name STATUS Sets various status bits. The STATUS field contains the following control bits: 16 FFPD FFPD = DMA FIFO buffer Full Packet Discard. EPD = Early Packet Discard occurred. A partially reassembled CPCS-PDU has been discarded FW = Firewall error condition occurred ...
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... This implements echo suppression of superfluous multi-broadcast LANE traffic on the ATM network. 5-54 ATM ServiceSAR Plus with xBR Traffic Management Figure 5-18 (Table holds 32 LECIDs) DPRI LECIDn+ LECIDn+ (etc.) Function/Description Mindspeed Technologies ™ RS8234 includes unique identifiers Table 5-34 and Table 5-35 display LECIDn LECIDn+ (etc.) 100074_039 LECID0 ... LECID30 ...
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... RS8234 ATM ServiceSAR Plus with xBR Traffic Management 5.7.7 Global Time-out Table This table exists in internal SRAM starting at address 0x1340. The values in this table should be initialized during system initialization, before reassembly processing is started. These values set the selectable hardware PDU timeout values as described in and field definitions for the Global Time-out Table ...
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... Reassembly Internal SRAM is in the address Description Status Queue 0 Base Table Status Queue 1 Base Table Status Queue 31 Base Table Free Buffer Queue 0 Base Table Free Buffer Queue 1Base Table Free Buffer Queue 31Base Table Other Internal Reassembly Registers: Global Time-out Table Mindspeed Technologies ™ RS8234 28234-DSH-001-B ...
Page 161
... Table 6-1 Specification (i.e., traffic parameters, QoS parameters, and feedback characteristics), and identifies whether the RS8234 supports these for each service category. The shaded areas are not indicative that the service category and attribute are undefined for the SAR — they simply indicate that the TM 4.1 Specification does not detail them ...
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... This specification models ABR to align with the TM 4.1 ABR specification. The RS8234 supports the rate based flow control and service models specified for ABR in TM 4.1. ...
Page 163
... RS8234 schedules all other traffic dynamically. The proprietary dynamic scheduling algorithm uses the remaining bandwidth to statistically multiplex all other service classes onto the line. The RS8234 can manage VCC traffic on either level. As well, it can schedule traffic as a CBR tunnel (or pipe), i.e., several VCCs assigned to a single CBR scheduling priority, with individual VCCs within that tunnel scheduled based on their traffic parameters ...
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... Traffic Management 6.1 Overview 6.1.2 ABR Flow Control Manager The RS8234 implements the ATM Forum ABR flow control algorithms, referred to in the aggregate as ABR by this document. The ABR service category effectively allows zero cell loss transmission through an ATM network, by regulating transmission based upon network feedback. The ABR algorithms regulate the rate of each VCC independently. diagram of the RS8234’ ...
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... Cell Scheduler Functional Description 6.2.1 Scheduling Priority 6.2.1.1 16 Priority The RS8234 supports 16 scheduling priorities (the “PRI” field in the SEG VCC Levels + CBR Table entry), in addition to the optional CBR service category, with “15” being the highest priority, down to “0” being the lowest priority. CBR channels are assigned a priority which is in effect higher than the 16 scheduling priorities dis- cussed here ...
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... SCHEDULE TABLE Mindspeed Technologies ™ RS8234 Assigned VCC_INDEX(es) SLOT INDEX } Words ( Octets) 29 SCHEDULE SLOT 100074_042 28234-DSH-001-B ...
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... RS8234 ATM ServiceSAR Plus with xBR Traffic Management If the USE_SCH_CTRL bit is asserted, the user controls the size and format of all schedule slots through the SLOT_DEPTH, 4-bit VBR_OFFSET, and TUN_PRI0-OFFSET fields in the SCH_CTRL register, as well as the CBR_TUN bit in the SEG_CTRL register. If the USE_SCH_CTRL bit in the SEG_CTRL ...
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... ATM ServiceSAR Plus with xBR Traffic Management VBR_OFFSET = 5 – illustrates how these priorities are assigned to the VBR fields. VCC_Index (PRI=VBR_OFFSET+0) VCC_Index (PRI=VBR_OFFSET+0) VCC_Index (PRI=VBR_OFFSET+2) Mindspeed Technologies ™ RS8234 Figure 6-4. The SAR can CBR_TUN = 0, DBL_SLOT = 0 VBR VBR VCC_Index (PRI=VBR_OFFSET+1) CBR_TUN = 0, DBL_SLOT = 1 VBR VBR ...
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... RS8234 ATM ServiceSAR Plus with xBR Traffic Management 6.2.2.4 Schedule Slot When USE_SCH_CTRL is asserted, the SLOT_DEPTH and VBR_OFFSET Formats With fields in the SCH_CTRL register plus the CBR_TUN field in the SEG_CTRL USE_SCH_CTRL register, dictate the format of each schedule slot. This format is illustrated in Asserted Figure Figure 6-5 ...
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... In this illustration, the number of VBR/ABR priorities = 3. In addition, the tunnel at PRI=5 has shared VBR traffic. CBR_TUN = 1, SLOT_DEPTH = 001. The highest VBR/ABR scheduling priority (PRI Thus, VBR_OFFSET = 1. Figure 6-6. One Possible Scheduling Priority Scheme with the RS8234 Scheduling Priority High VBR_OFFSET ...
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... SLOT_PER (slot period) field of the SCH_SIZE register. 6.2.3.1 CBR Rate Maximum Rate Selection For each CBR assigned cell slot, the RS8234 generates one cell on the specified VCC. The maximum or base rate of CBR channels is determined by the duration of a cell slot according to the equation below, where R cells per second. ...
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... R/TBL_SIZE, or 3.54 K cells/second. Not all cell slots have been assigned to CBR channels. During these slots, the RS8234 will dynamically schedule traffic from the other service classes. However, the total bandwidth of channels A, B, and C will be reserved ...
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... CBR traffic. However, no system is without some CDV. In the case of terminals using the RS8234, the dominant factor in CDV is the variation introduced between the segmentation coprocessor and the PHY layer device at the Transmit FIFO (TX_FIFO) ...
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... CDV = 1 (CBR rate in cells sec) + max 6.2.2.4). TX_FIFO_LEN > (worst case PCI latency) (line rate in cells sec) Mindspeed Technologies ™ RS8234 6-10. In this example, the 100074_049 TX_FIFO_LEN (line rate in cells sec) 28234-DSH-001-B ...
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... The host requests this rate matching adjustment by setting the SCH_OPT bit of the CBR channel. The next time the RS8234 encounters a CBR slot for this VCC, it will not transmit data on that VCC. Then the RS8234 indicates to the host that a slot has been skipped by clearing the SCH_OPT bit. ...
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... Mapping The ATM Forum TM 4.1 Specification describes the different categories of VBR RS8234 VBR Service service in a different manner than is employed in the RS8234 device. These Categories to TM 4.1 relationships are described here: Table 6-3. RS8234 VBR to TM 4.1 VBR Mapping VBR Service Categories ...
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... RS8234 ATM ServiceSAR Plus with xBR Traffic Management 6.2.4.5 CLP-Based The third option allows both buckets to apply to CLP=0 cells. CLP=0 means high Buckets priority cells; CLP=1 means cells are subject to discard. CLP=1 cells are scheduled from the second bucket only. Therefore, the second bucket should correspond to PCR ...
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... If both non-tunnel and tunnel scheduling priorities exist, the host must assign the highest priority level(s) to CBR tunnel(s). 6-18 ATM ServiceSAR Plus with xBR Traffic Management The format of a CBR tunnel schedule table slot is not backward- compatible with the CBR tunnel format used in the Bt8233 SAR. Mindspeed Technologies ™ RS8234 28234-DSH-001-B ...
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... WAN service provider. The purchaser can then dynamically manage the traffic within this leased CBR tunnel as CBR and/or a combination of other service categories. In this example, the user has configured the RS8234 to manage two independent tunnels. The first tunnel priority five, is through a private ATM network, perhaps a corporate ATM campus backbone. The other tunnel, priority six, carries traffic through a public network ...
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... Traffic Management 6.2 xBR Cell Scheduler Functional Description Figure 6-11. Another Possible Scheduling Priority Scheme with the RS8234 Priority Tunnel A Levels 15 rt-VBR HIGH VBR_OFFSET nrt-VBR LOW 6-20 ATM ServiceSAR Plus with xBR Traffic Management Example of Multi-Service Tunnels ...
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... An additional level of traffic shaping can be established on GFR-UBR priority queues by shaping to a specified PCR. (See 6.2.8 PCR Control for Priority Queues The RS8234 provides an optional method of creating tunnels (i.e., of limiting the bandwidth of a group of channels), by allowing the user to assign a PCR to a scheduling priority queue, so that the aggregate of the rates of the channels assigned to that priority queue will not be greater than the PCR assigned ...
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... Forum’s TM 4.1 specification before attempting to understand the RS8234’s ABR implementation. 6.3.2 Internal ABR Feedback Control Loop As a complete implementation of the UNI ATM layer, the RS8234 acts as both an ABR Source and Destination, complying with all required TM 4.1 ABR behaviors. The RS8234 utilizes the dynamic rate adjustment capability of the xBR Cell Scheduler as the Source’ ...
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... Source Flow Figure 6-13 Control Feedback The RS8234 injects an in-rate cell stream (CLP = 0) into the ATM network for each ABR VCC. Network elements modify the flow control fields in the cell stream’s Forward RM cells. After a round trip through the network and destination node, these cells return to the RS8234 receive port as Backward RM cells ...
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... Traffic Management 6.3 ABR Flow Control Manager 6.3.2.2 Destination The RS8234 also responds to an incoming ABR cell stream as an ABR Behavior Destination. The reassembly coprocessor processes received Forward RM cells. It turns around this incoming information to the segmentation coprocessor via the SCH_STATE part of the segmentation VCC Table entry. The segmentation coprocessor then formats Backward RM cells containing this information and inserts these turnaround RM cells into the transmit cell stream ...
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... Cell Type Decisions 6.3.6.1 In-rate Cell Since every ABR connection in a network is full duplex, the RS8234 is a Source Streams and a Destination for each VCC. The RS8234 multiplexes user data cells, Forward RM cells, and Backward RM cells into the in-rate ABR cell stream. ...
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... Furthermore, since immature specification, the rules for cell interleaving of in-rate cell streams may be modified slightly. The RS8234 provides a programmable mechanism to comply with TM 4.1’s specification on cell stream interleaving. This Cell Type Decision algorithm makes on-the-fly decisions concerning which type of cell to send, based on the current state of the connection ...
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... Whenever the RS8234 transmits an in-rate Forward RM cell, it copies FWD_INDEX to CELL_INDEX. Run-time Operation Each time an ABR cell transmit opportunity arises, the RS8234 makes a cell decision. The SAR retrieves CELL_INDEX from SCH_STATE and chooses a Cell Type Action location within the current ACDB. Table 6-4 shows the four conditions which are used to form this vector ...
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... Control Manager state machine will select a cell type by indexing into the ACDB according to the ACDV . In this case, the only condition present is RUN=1, so ACDV = 0001b. Cell Type Action Index 1 is selected. For this ACDB, Cell Type Action 1 is DATA or “Send Data Cell”. Therefore, the RS8234 will transmit a user data cell. ...
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... The ABR Flow Control Manager uses all of these inputs to calculate the ACR of the connection. This ACR corresponds to I and L GCRA parameters. The RS8234 updates the I and L parameters of the VCC with the new ACR I and L values. The Flow Control Manager updates the transmission rate in response to two types of events— ...
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... The RS8234 computes both rate candidates by first mapping all rate parameters into rate index space. Since rate indexes are a monotonically increasing function of rate, the RS8234 selects the candidate with the lowest rate index. For the RR algorithm, the conversion is embedded in the ARDBs themselves. ...
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... Backward RM cell into rate index space. This mapping converts the floating point ER field rate representation to an absolute rate index. Note that this mapping does not depend on the current rate of the connection. The RS8234 maps ER field to rate indexes with a programmable piece-wise linear function. Each piece-wise linear segment is described in the ABR Exponent Table ...
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... ABR Flow Control Manager Figure 6-20. Explicit Rate (ER) RATE_INDEX Candidate Selection ER Once both candidates are identified, the RS8234 selects the smaller of the two, each of which are RATE_INDEX in the VCC’s SCH_STATE entry. Then the RS8234 uses this RATE_INDEX to point to the corresponding appropriate RDB and, as specified in TM 4.1, updates the VCC’ ...
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... RS8234 ATM ServiceSAR Plus with xBR Traffic Management Figure 6-21. Dynamic Traffic Shaping from RM Cell Feedback Backward_ RM Cell Reassembly Coprocessor ER Segmentation VCC Table SCH_STATE RATE_INDEX CURRENT RATE Update NOTE(S): The RR RATE_INDEX and ER RATE_INDEX results are implicitly > MCR. 28234-DSH-001-B RSM/SEG Queue ...
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... PCR. This is because when a Forward RM cell is eventually received as a Backward RM cell, the RS8234 will map the available cell rate (ACR rate specified by the exponent table. If PCR falls between two exponent table rates and FWD_ER is set to PCR, the ACR of the connection will be limited to the lower of the two exponent table rates, thereby lowering the rate below PCR ...
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... When the actual cell rate on a channel has lowered to the point where scheduling of the VCC has halted, and SET_OOR at that rate = 1, the RS8234 sets the SCH_OOR bit in the VCC’s SCH_STATE to a logic high. The RS8234 will then generate an out-of-rate Forward RM cell on that channel. ...
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... The GFC protocols are defined and described in ITU Recommendation I.361. 6.4.2 The RS8234’s Implementation of GFC The RS8234 implements the GFC one-queue mode. The reassembly coprocessor provides Auto Configure and Command Detection. The segmentation coprocessor provides Halt Processing and Per-transmit Queue SET_A control. It does not implement the optional Queue B ...
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... RS8234 ATM ServiceSAR Plus with xBR Traffic Management 6.4.2.1 Configuring the The following describes an example sequence of how to auto-configure a link for Link for GFC Operation GFC operation after the link has been initialized 10. 28234-DSH-001-B Host sets a software GFC initialization timer = 0. ...
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... Def. 6-38 ATM ServiceSAR Plus with xBR Traffic Management (Reserved for 1 VBR/ABR pointer) (Reserved for 2 16-bit VBR/ABR pointers CBR_VCC_INDEX (15 bits PRI2 Mindspeed Technologies ™ RS8234 Table 6-5. Table 6- Table 6-7. The Table 6- ...
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... RS8234 ATM ServiceSAR Plus with xBR Traffic Management Table 6-8. Schedule Slot Field Descriptions — CBR Traffic Field Name CBR Set high to indicate a CBR slot; set low to indicate a tunnel slot. PRI3 Specifies the highest priority of four possible scheduling priority queues to service when a scheduling slot for this CBR tunnel becomes active ...
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... BUCKET2 L1_EXP 7 (MSB) BUCKET2 8 (LSB) 9 6-40 ATM ServiceSAR Plus with xBR Traffic Management Description and Table 6-12 the SCH_STATE part of the Segmentation VCC Table Section 6.2.4, VBR Traffic, for key data on I and L values. L1_MAN I1_EXP Reserved Reserved Mindspeed Technologies ™ RS8234 I1_MAN 28234-DSH-001-B ...