ATA6020N ATMEL Corporation, ATA6020N Datasheet
ATA6020N
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ATA6020N Summary of contents
Page 1
... Code-efficient Instruction Set – High-level Language Programming with qFORTH Compiler 1. Description The ATA6020N is a member of Atmel’s 4-bit single-chip microcontroller family. It con- tains ROM, RAM, parallel I/O ports, one 8-bit programmable multifunction timer/counter with modulator function, voltage supervisor, interval timer with watchdog function and a sophisticated on-chip clock generation with external clock input and integrated RC-oscillators ...
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... NC – Not connected NC – Not connected OSC1 I Oscillator input ATA6020N 2 1 VDD 2 BP40/INT3/SC 3 BP53/INT1 4 BP52/INT1 5 BP51/INT6 ATA6020N 6 BP50/INT6 OSC1 Alternate Function – – – – NTE test mode enable, see also section ''Master Reset'' – – – SC serial clock or INT3 external ...
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... Introduction The ATA6020N is a member of Atmel’s 4-bit single-chip microcontroller family. It contains ROM, RAM, parallel I/O ports, one 8-bit programmable multifunction timer/counter, voltage supervisor, interval timer with watchdog function and a sophisticated on-chip clock generation with inte- grated RC-oscillators. 4. MARC4 Architecture General Description The MARC4 microcontroller consists of an advanced stack-based, 4-bit CPU core and on-chip peripherals ...
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... The corresponding memory map is shown in held in ROM and are accessed via the MARC4's built-in TABLE instruction. Figure 4-2. 7FFh 1FFh 000h ATA6020N 4 Figure ROM Map of ATA6020N ROM ( bit) Zero page 4-2. Look-up tables of constants can also be 1F8h 1F0h 1E8h 1E0h 1E0h ...
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... RAM The ATA6020N contains 256 x 4-bit wide static random access memory (RAM), which is used for the expression stack. The return stack and data memory are used for variables and arrays. The RAM is addressed by any of the four 8-bit wide RAM address registers SP, RP, X and Y. ...
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... The return stack pointer increments and decrements in steps of 4. This means that every time a 12-bit element is stacked, a 4-bit RAM location is left unwritten. This location is used by the qFORTH compiler to allocate 4-bit variables. After a reset the return stack pointer has to be initialized via >RP FCh. ATA6020N 6 0 Program counter ...
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... After a reset or on executing the DI instruction, the interrupt enable flag is reset thus disabling all interrupts. The core will not accept any further interrupt requests until the interrupt enable flag has been set again by either executing SLEEP instruction. 4708D–4BMCU–09/05 ATA6020N 7 ...
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... CCR. An interrupt occurrence will still be registered, but the interrupt routine only starts after the I-flag is set. All interrupts can be masked, and the priority individually software configured by programming the appropriate control register of the interrupting module (see section ATA6020N 8 ALU Zero-address Operations RAM ...
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... INT7 INT7 active RTI INT5 INT5 active RTI INT2 INT2 pending Time RTI INT2 active RTI SWI0 INT0 pending INT0 active RTI Main / Autosleep ATA6020N 9 ...
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... Hardware Interrupts In the ATA6020N, there are eleven hardware interrupt sources with seven different levels. Each source can be masked individually by mask bits in the corresponding control registers. An over- view of the possible hardware configurations is shown in ATA6020N ...
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... NRST 4.2.1 Power-on Reset and Brown-out Detection The ATA6020N has a fully integrated power-on reset and brown-out detection circuitry. For reset generation no external components are needed. These circuits ensure that the core is held in the reset state until the minimum operating supply voltage has been reached. A reset condition will also be generated should the supply voltage drop momentarily below the minimum operating level except when a power-down mode is acti- vated (the core is in SLEEP mode and the peripheral clock is stopped) ...
Page 12
... External Clock Supervisor The external input clock supervisor function can be enabled if the external input clock is selected within the CM- and SC-registers of the clock module. The CPU reacts in exactly the same man- ner as a reset stimulus from any of the above sources. ATA6020N 12 Brown-out Detection ...
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... Voltage Monitor V Voltage monitor BP41/ IN VMI VMC VM2 VM1 VM0 VMST - - Bit 3 Bit 2 Bit 1 VM2 VM1 VM0 — — reserved ATA6020N DD INT7 OUT VIM res VMS Primary register address: ’F’hex Bit 0 VIM Reset value: 1111b VMS Reset value: xx11b 13 ...
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... VIM = 1, voltage monitor interrupt is disabled VMS Voltage Monitor Status bit • VMS = 0, the voltage at the comparator input is below V • VMS = 1, the voltage at the comparator input is above V Figure 4-10. Internal Supply Voltage Supervisor Figure 4-11. External Input Voltage Supervisor ATA6020N 14 Voltage Monitor Modes VM1 VM0 Function ...
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... Clock Generation 4.4.1 Clock Module The ATA6020N contains a clock module with two different internal RC-oscillator types. OSC1 can be used as input for external clocks or to connect an external trimming resistor for RC-oscil- lator 2. All necessary circuitry, except the trimming resistor, is integrated on-chip. One of these oscillator types or an external input clock can be selected to generate the system clock (SYSCL) ...
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... The modes for clock sources are programmable with the OS1-bit and OS0-bit in the SC-register and the CCS-bit in the CM-register. 4.4.2 Oscillator Circuits and External Clock Input Stage The ATA6020N consists of two different internal RC-oscillators and one external clock input stage. 4.4.2.1 RC-oscillator 1 Fully Integrated For timing insensitive applications possible to use the fully integrated RC-oscillator 1 ...
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... (see Figure ext OSC1 R ext Ext. input clock RcOut1 ExOut ExIn Osc-Stop Stop CCS Clock monitor Res CCS Supervisor Reset Output (Res) 0 Enable 1 Disable x Disable . In this configuration, the RC-oscil 3.5V to 5.5V. 4-15). RC-oscillator 2 RcOut2 RcOut2 R Trim Osc-Stop Stop ATA6020N 17 ...
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... CCS CSS1 CSS0 Table 4-6. 4.4.3.2 System Configuration Register (SC) SC: write BOT OS1 OS0 ATA6020N 18 Bit 3 Bit 2 Bit 1 NSTOP CCS CSS1 Not STOP peripheral clock NSTOP = 0, stops the peripheral clock while the core is in SLEEP mode NSTOP = 1, enables the peripheral clock while the core is in SLEEP mode ...
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... V DD The ATA6020N has various power-down modes. During the sleep mode the clock for the MARC4 core is stopped. With the NSTOP-bit in the clock management register (CM pro- grammable if the clock for the on-chip peripherals is active or stopped during the sleep mode. If the clock for the core and the peripherals is stopped the selected oscillator is switched off ...
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... Addr. (ASW) = Auxililiary Switch Module Address Addr. (Mx) = Module Mx Address Addr. (SPort) = Subport Address Prim._Data = Data to be written into Primary Register Aux._Data = Data to be written into Auxiliary Register Aux._Data (lo) = Data to be written into Auxiliary Register (low nibble) ATA6020N 20 Example of I/O Addressing Module M1 (Address Pointer) Bank of Subaddress Reg ...
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... Serial interface status/control register W 1111b Serial interface control register 2 Reserved Reserved W 0000b ROM bank switch register — Reserved W 1111b Voltage monitor control register R xx11b Voltage monitor status register ATA6020N Module Type See Page ...
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... Figure 5-2. Bi-directional Port 2 I/O Bus I/O Bus Master reset I/O Bus ATA6020N 22 4-bit wide bitwise-programmable I/O port. 4-bit wide bitwise-programmable bi-directional port with optional static pull-ups and programmable interrupt logic. 4-bit wide bitwise-programmable bi-directional port also provides the I/O interface to Timer 2, SSI, voltage monitor input and external interrupt input. ...
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... BP21 in output mode BP22 in input mode BP22 in output mode BP23 in input mode BP23 in output mode 24). The interrupts (INT1 and INT6) can be masked or independently configured 20). ATA6020N Primary register address: ’2’hex Bit 0 P2DAT0 Reset value: 1111b Auxiliary register address: ’2’hex Bit 0 ...
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... D P5DATy Master reset IN enable Figure 5-4. Port 5 External Interrupts Data in BP52 Bi-directional Port IN_Enable I/O-bus Data in BP53 Bi-directional Port IN_Enable P5CR ATA6020N (1) Q (1) S (1) Mask options INT1 INT6 Decoder Decoder Decoder P53M2 P53M1 P52M2 P52M1 P51M2 P51M1 P50M2 P50M1 ...
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... Figure 5-2 on page ATA6020N Primary register address:’5’hex Bit 0 P5DAT0 Reset value: 1111b Auxiliary register address:’5’hex Bit 0 P50M1 Reset value: 1111b Bit 4 ...
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... BP41 in input mode BP41 in output mode BP41 enable alternate function (VMI for voltage monitor input) BP41 enable alternate function (T2I external clock input for Timer 2) ATA6020N 26 PxMRy V DD (1) (1) (1) Mask options Bit 1 Bit 0 ...
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... SUBCL Timer 1 MUX Timer 2 T1OUT 4-bit Counter 2/1 MUX Compare 2/1 POUT T2I 8-bit Counter 2/2 MUX DCG Compare 2/2 TOG2 Receive-buffer MUX 8-bit Shift-register Transmit-buffer Watchdog NRST INT2 Interval/Prescaler Modu- lator 2 I/O bus Control INT4 SSI SCL Control INT3 ATA6020N T2O ...
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... Figure 5-7. Figure 5-8. Timer 1 and Watchdog T1C1 T1RM T1C2 T1C1 T1C0 3 Write of the T1C1 register Decoder RES CL1 CL Decoder WDC WDL WDR WDT1 WDT0 ATA6020N 28 Timer 1 Module SYSCL CL1 14-bit MUX Prescaler SUBCL T1CS MUX for interval timer Q11 Q6 ...
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... Time Interval with SYSCL Clock Management Tin 32 Tin 64 Tin 128 Tin 256 Tin 512 Tin 4096 Tin 32768 Tin 262144 15) ATA6020N = 2/1 MHz 1 µs/2 µs 2 µs/4 µs 4 µs/8 µs 8 µs/16 µs 16 µs/32 µs 128 µs/256 µs 1024 µs/2048 µs 8192 µs/16384 µs 29 ...
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... Watchdog Control Register (WDC) WDC Bit 3 = MSB, Bit 0 = LSB WDL WDR WDT1 WDT0 Both these bits control the time interval for the watchdog reset Table 5-6. Note: ATA6020N 30 Bit 3 Bit 2 Bit 1 – T1BP T1CS Timer 1 SUBCL ByPassed T1BP = 1, TIOUT = T1MUX T1BP = 0, T1OUT = SUBCL ...
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... For 12-bit compare data value For 8-bit compare data value For 4-bit compare data value 4708D–4BMCU–09/05 ATA6020N 0 x 4095 0 y 255 ...
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... The duty cycle gener- ator (DCG) has to be bypassed in this mode. Figure 5-10. 12-bit Compare Counter CL2/1 4-bit counter RES 4-bit compare CM1 4-bit register T2D1, 0 ATA6020N 32 P4CR T2M1 CL2/2 DCG OVF1 POUT RES Control ...
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... RES CM2 8-bit compare 8-bit register T2RM T2OTM 4-bit counter RES CM1 4-bit compare 4-bit register Timer 2 output mode and T2OTM-bit T2OTM T2IM T2CTM DCGO TOG2 INT4 Timer 2 output mode and T2OTM-bit T2IM T2CTM POUT ATA6020N DCGO TOG2 INT4 33 ...
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... OMSK 5.2.6.3 Timer 2 Output Signals Timer 2 Output Mode 1 Toggle Mode Timer 2 compare match toggles the output flip-flop (M2) -> T2O Figure 5-14. Interrupt Timer/Square Wave Generator — Output Toggles with Each Edge Com- Counter 2 Counter 2 ATA6020N 34 Toggle S1 RES/SET T2M2 T2OS2 T2TOP pare Match Event ...
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... Figure 5-16. Pulse Generator — Timer Toggles with Timer Overflow and Compare Match Counter 2 Counter 2 4708D–4BMCU–09/05 Input T2R CMx INT4 T2O Toggle by start T2O Input T2R CMx OVF2 INT4 T2O 4095 255 4095 255 ATA6020N ...
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... TOG2 Timer 2 Output Mode 4 Bi-phase Modulator: Timer 2 modulates the SSI internal data output (SO) to Bi-phase code. Figure 5-19. Bi-phase Modulation ATA6020N ...
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... OVF2 load the next compare value INT4 T2O “Addressing Peripherals” on page 8-bit SR-Data 100 255 0 150 255 0 50 T2CO2=150 load load 20. The alternate functions of the Ports ATA6020N 1 Bit 0 Bit 0 255 0 100 ...
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... T2CS1 T2CS0 Table 5-7. T2CS1 T2TS T2R 5.2.6.6 Timer 2 Mode Register 1 (T2M1) T2M1 T2D1 T2D0 Table 5-8. T2MS1 T2MS0 ATA6020N 38 Bit 3 Bit 2 Bit 1 T2CS1 T2CS0 T2TS Timer 2 Clock Select bit 1 Timer 2 Clock Select bit 0 Timer 2 Clock Select Bits T2CS0 Input Clock (CL 2/1) of Counter Stage 2/1 0 ...
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... DCGIN DCGO0 DCGO1 DCGO2 DCGO3 ATA6020N Timer 2 Modes 12-bit compare counter, the DCG have to be bypassed in this mode 8-bit compare counter with 4-bit programmable prescaler and duty cycle generator 8-bit compare counter clocked ...
Page 40
... In the 12-bit timer mode, T2CO1 contains bits and T2CO2 bits the 12-bit com- pare value. In all other modes, the two compare registers work independently as a 4-bit and 8-bit compare register. When assigned to the compare register a compare event will be suppressed. ATA6020N 40 Bit 3 ...
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... Compare match (CM2) x Overflow (OVF2) 1 Compare match (CM2) Address: ’7’hex – Subaddress: ’4’hex Bit 2 Bit 1 Bit 0 Reset value: 1111b Address: ’7’hex – Subaddress: ’5’hex Reset value: 1111b Bit 2 Bit 1 Bit 0 Reset value: 1111b Bit 6 Bit 5 Bit 4 ATA6020N 41 ...
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... The modulating data is converted by the SSI into a continuous serial stream of data which is in turn modulated in one of the timer functional blocks. Figure 5-23. Block Diagram of the Synchronous Serial Interface T1OUT SYSCL ATA6020N 42 I/O-bus SIC1 SIC2 SC ...
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... MCL stop or start conditions are cur- rently being generated. Both the current SRDY and ACT status can be read in the SSI status register. To deactivate the SSI, the SIR bit must be set high. 4708D–4BMCU–09/05 ATA6020N 43 ...
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... Care should be taken to read out the final complete 8-bit data telegram of a multiple word message before deactivating the SSI (SIR = 1) and termi- nating the reception. After termination, the shift register contents will overwrite the receive buffer. ATA6020N 44 SC (rising edge) ...
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... Write STB Write STB (tx data 2) (tx data 3) lsb msb data 3 Read SRB Read SRB (rx data 1) (rx data 2) ATA6020N lsb 0 lsb Read SRB (rx data 3) 45 ...
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... SIR bit. So, if the SIR-bit is set to “1” in with telegram, the SSI will complete the current transfer and terminate the dialog with an MCL stop condition. Figure 5-27. Example of MCL Transmit Dialog Interrupt (IFN = 0) Interrupt (IFN = 1) Figure 5-28. Example of MCL Receive Dialog Interrupt (IFN = 0) Interrupt (IFN = 1) ATA6020N 46 Start SC msb lsb data 1 SRDY ACT ...
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... A LOW to HIGH transition of the SD line while the clock (SC) is HIGH defines a STOP condition. The state of the data line represents valid data when, after START condition, the data line is stable for the duration of the HIGH period of the clock signal. ATA6020N (3) (1) Stop condition 47 ...
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... SSI transmit buffer. This in turn, enables shift clocks to the prescaler when this final word is shifted out. On reaching the compare value, the prescaler trig- gers the OMSK signal and all following data bits are blanked. ATA6020N 48 All address and data words are serially transmitted to and from the device in eight-bit words ...
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... Note: with SCD = '0' the bits SCS1 and SCS0 are insignificant Serial Clock Source Select Bits SCS1 SCS0 Internal Clock for SSI 1 1 SYSCL T1OUT POUT TOG2/2 ATA6020N OMSK SO Control Output SI LSB Auxiliary register address: ’9’hex Bit 0 SCS0 Reset value: 1111b 49 ...
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... Serial Interface Control Register 2 (SIC2) SIC2 MSM SM1 SM0 Table 5-13. Mode SDD SDD controls port directional control and defines the reset function for the SRDY-flag ATA6020N 50 Bit 3 Bit 2 Bit 1 MSM SM1 SM0 Modular Stop Mode MSM = 1, modulator stop mode disabled (output masking off) MSM = 0, modulator stop mode enabled (output masking on) - used in modulation modes for generating bit streams which are not sub– ...
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... Reset value: 1111b SRDY Reset value: xxxxb Primary register address: ’9’hex Bit 2 Bit 1 Bit 0 Reset value: xxxxb Bit 6 Bit 5 Bit 4 Reset value: xxxxb Primary register address: ’9’hex Bit 6 Bit 5 Bit 4 Reset value: xxxxb Bit 2 Bit 1 Bit 0 Reset value: xxxxb ATA6020N 51 ...
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... Combination Mode Timer 2 and SSI Figure 5-32. Combination Timer 2 and SSI T2I SYSCL CL2/1 T1OUT 4-bit Counter 2/1 reserved SCL RES T2C I/O-bus ATA6020N 52 P4CR T2M1 DCGO CL2/2 DCG OVF1 POUT Compare 2/1 Timer 2 - control POUT CM1 T2CO1 ...
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... The Modulator 2 of Timer 2 modulates the SSI internal data out put to Bi-phase code TOG2 Bit T2O Data: 00110101 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 8-bit SR-data Bit ATA6020N Bit 12 Bit 13 53 ...
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... SSI is used as stop signal for the modulator. 12-bit Manchester telegram. Figure 5-36. Manchester Modulation 2 Buffer full Counter 2/1 ATA6020N 54 8-bit shift register internal data output (SO) to Timer 2 modulator stage 8-bit compare counter with 4-bit programmable prescaler The Modulator 2 of Timer 2 modulates the SSI internal ...
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... SIR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit MSM Timer 2 Mode 3 SCL Counter 2/1 = Compare Register 2 2/1 OMSK T2O Figure 5- ATA6020N is an example for ...
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... RC-oscillator active) Sleep current (CPU sleep, RC-oscillator inactive 5.5V 0V –40°C to +85°C unless otherwise specified amb Parameters Active current CPU active Power down current (CPU sleep, RC oscillator active) ATA6020N Symbol short T amb T stg ...
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... IL –50 –100 100 –120 –250 I IL –300 –600 120 250 I IH 300 600 –3 –5 OH –8 –16 ATA6020N Max. Unit 3 Max. Unit 0 –50 µA –200 µA 50 µA 200 µA – ...
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... EXSCL at OSC1 input Input HIGH time Reset Timing Power-on reset time RC-oscillator 1 Frequency Stability Stabilization time RC-oscillator 2 – External Resistor Frequency Stability Stabilization time External resistor ATA6020N 58 Test Conditions V = 2. – +85 C amb = 0V 25°C unless otherwise specified. amb Test Conditions Rise/fall time < ...
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... System Clock (kHz) Active Supply Current versus V DD 0.600 MHz SYSCLK 0.500 0.400 0.300 0.200 0.100 0.000 2.0 2.5 3.0 3.5 4.0 V (V) DD ATA6020N 2500 3000 3500 4000 1200 1400 1600 1800 2000 T = 85° ...
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... Figure 8-4. Figure 8-5. Figure 8-6. ATA6020N 60 Power-down Supply Current versus V 90 500 kHz 80.0 SYSCL T = 25°C 70.0 amb 60.0 50.0 40.0 30.0 20.0 10.0 0.0 2.0 2.5 3.0 3.5 4.0 V (V) DD Internal RC Frequency versus V DD 5.60 5.40 5.20 5.00 4.80 4.60 4.40 4.20 4.00 3.80 3.60 3.40 3.20 3.00 25°C 2.80 2.60 2.40 2.20 2.00 2.0 2.5 3.0 3.5 4.0 V (V) DD External RC Frequency versus V DD 1.730 R = 43k 1.710 ext 1.690 1.670 1.650 1.630 1.610 1.590 1.570 2.0 2.5 3.0 3.5 4 4.5 5.0 5.5 6.0 6 -40°C amb 85° ...
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... External RC Frequency versus T 1.730 R = 43k 1.710 ext 1.690 V DD 1.670 1.650 1.630 1.610 1.590 1.570 -40 -30 -20 - amb ATA6020N DD 4.5 5.0 5.5 6 (°C) amb amb = 6 (° ...
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... Figure 8-10. External RC Frequency versus R Figure 8-11. Pull-up Resistor versus V Figure 8-12. Strong Pull-up Resistor versus V ATA6020N 62 ext 5500 25°C amb 4500 3500 2500 max 1500 min 500 ext DD 1000 85°C amb 100.0 10.0 2.0 2.5 3.0 3.5 4.0 4.5 V (V) ...
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... Figure 8-15. Strong Pull-down Resistor versus V 4708D–4BMCU–09/05 - Output High Voltage -5.0 -10.0 3.0 V -15.0 -20.0 -25 25°C amb -30.0 -35.0 -40.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3 1000 85°C amb 100 -40°C 10 2.0 2.5 3.0 3.5 4.0 4 100 85°C amb -40°C 10.0 2.0 2.5 3.0 3.5 4.0 4.5 V (V) DD ATA6020N 4.0 V 5.0 V 6.5 V 4.5 5.0 5.5 6.0 6.5 25°C 5.0 5.5 6.0 6.5 25°C 5.0 5.5 6.0 6.5 63 ...
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... Figure 8-16. Output Low Current versus Output Low Voltage Figure 8-17. Output High Current versus T Figure 8-18. Output Low Current versus T ATA6020N 25° 6.5 V amb 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4 25°C, V amb 0 -5 -10 -15 -20 -25 -40 -30 -20 - ...
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... I/O activities. Figure 8-19. MARC4 Emulation MARC4 emulator Program memory Trace memory Control logic Personal computer 4708D–4BMCU–09/05 MARC4 emulation-CPU I/O bus CORE I/O control Emulation control Port 0 Port 1 SYSCL/ TCL, TE, NRST ATA6020N Emulator target board MARC4 target chip CORE (inactive) Peripherals Application-specific hardware 65 ...
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... BP43 [ ] CMOS [ ] Pull- Open drain [ Pull-down [ ] Open drain [ Pull-up static [ ] Pull-down static Please attach this page to the approval form. Date: ____________ Signature: _________________________ Company: _________________________ ATA6020N 66 Input Port 5 Pull-down static ECM (External Clock Monitor) Watchdog Used oscillator Output Input BP50 [ ] CMOS ...
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... Extended Type Number ATA6020x-yyy-TKQY Note Hardware revision yyy = Customer specific ROM-version 11. Package Information Package SSO20 Dimensions in mm 0.25 0. 4708D–4BMCU–09/05 Program Memory Data-EEPROM 2 kB ROM No 6.75 6.50 1.30 0.15 0.05 5.85 11 technical drawings according to DIN specifications 10 ATA6020N Package Delivery SSO20, Pb-free Taped and reeled 5.7 5.3 4.5 4.3 0.15 6.6 6.3 67 ...
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... Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. 4708D-4BMCU-09/05 4708C-4BMCU-02/04 4708B-4BMCU-12/03 ATA6020N 68 History Put datasheet in a new template Pb-free Logo on page 1 added Ordering Information on page 67 changed Figure 4 “ROM MAP” on page 4 changed. ...
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... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © Atmel Corporation 2005. All rights reserved. Atmel marks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Atmel Operations Memory ...