ATA6020N ATMEL Corporation, ATA6020N Datasheet - Page 47

• Manufacturer Part Number: ATA6020N
• Description: Low-current Microcontroller For Watchdog Function
• Manufacturer: ATMEL Corporation

5.2.7.6
5.2.7.7
4708D–4BMCU–09/05
8-bit Pseudo MCL Mode
MCL Bus Protocol
In this mode, the SSI exhibits all the typical MCL operational features except for the acknowl-
edge-bit which is never expected or transmitted.
The MCL protocol constitutes a simple 2-wire bi-directional communication highway via which
devices can communicate control and data information. Although the MCL protocol can support
multi-master bus configurations, the SSI, in MCL mode is intended for use purely as a master
controller on a single master bus system. So all reference to multiple bus control and bus con-
tention will be omitted at this point.
All data is packaged into 8-bit telegrams plus a trailing handshaking or acknowledge-bit. Nor-
mally the communication channel is opened with a so-called start condition, which initializes all
devices connected to the bus. This is then followed by a data telegram, transmitted by the mas-
ter controller device. This telegram usually contains an 8-bit address code to activate a single
slave device connected onto the MCL bus. Each slave receives this address and compares it
with its own unique address. The addressed slave device, if ready to receive data will respond
by pulling the SD line low during the 9th clock pulse. This represents a so-called MCL acknowl-
edge. The controller on detecting this affirmative acknowledge then opens a connection to the
required slave. Data can then be passed back and forth by the master controller, each 8-bit tele-
gram being acknowledged by the respective recipient. The communication is finally closed by
the master device and the slave device put back into standby by applying a stop condition onto
the bus.
Figure 5-29. MCL Bus Protocol 1
Bus not busy (1)
Start data transfer (2)
Stop data transfer (3)
Data valid (4)
SC
SD
(1)
condition
Start
(2)
Both data and clock lines remain HIGH.
A HIGH to LOW transition of the SD line while the clock (SC)
is HIGH defines a START condition.
A LOW to HIGH transition of the SD line while the clock (SC)
is HIGH defines a STOP condition.
The state of the data line represents valid data when, after
START condition, the data line is stable for the duration of the
HIGH period of the clock signal.
Data
valid
(4)
change
Data
Data
valid
(4)
condition
Stop
(3) (1)
ATA6020N
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