WM8608 ETC-unknow, WM8608 Datasheet - Page 21

• Manufacturer Part Number: WM8608
• Description: The Wm8608 Comprises A High Performance Multi-channel Pwm Digital Power Amplifier Controller. Simply By Adding Appropriate Power Output Stages A Multi-channel Power Amplifier May Be Built. Six Identical Full Audio Bandwidth Channels, Plus A Reduced B
• Manufacturer: ETC-unknow

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MASTER CLOCK AND AUDIO SAMPLE RATES
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The WM8608 supports a wide range of master clock frequencies on the MCLK pin, and can generate
many commonly used audio sample rates directly from the master clock. (See Table 14 for details.)
Table 12 Clocking and Sample Rate Control (1)
If the WM8608 is running in MPEG mode (i.e. f
automatically if the SRDET bit is set. In this case, the SR bits do not need programming.
Table 13 Clocking and Sample Rate Control (2)
The clocking of the WM8608 is controlled using the CLKDIV2 and SR control bits. Setting the
CLKDIV2 bit divides MCLK by two internally. Each value of SR[3:0] selects one combination of
MCLK division ratios and hence one combination of sample rates (see next page). Since all sample
rates are generated by dividing MCLK, their accuracy depends on the accuracy of MCLK. If MCLK
changes the sample rates change proportionally.
R0 (00h)
Clocking
R1 (01h)
Sample Rate
REGISTER
REGISTER
ADDRESS
ADDRESS
0
1
2
3
3:0
4
BIT
BIT
CMAST
MPEG
MEDGE
CLKDIV2
SR [3:0]
SRDET
LABEL
LABEL
1
1
0
0
0000
1
DEFAULT
DEFAULT
XIN
= 27MHz) the sample can be detected
Master Clock Mode
0 = MCLK input
1 = XIN input
MPEG Mode
0 = see Table 14
1 = MCLK is 27MHz
Master Clock Active Edge
0 = positive edge
1 = negative edge
Master Clock Divide by 2
1 = MCLK is divided by 2
0 = MCLK is not divided
Sample Rate Control. Refer to
Table 14.
Sample rate detect
1 = Enabled
(in MPEG mode only)
0 = Disabled
DESCRIPTION
DESCRIPTION
PP Rev 1.5 March 2004
WM8608
21