WM8608 ETC-unknow, WM8608 Datasheet - Page 24

• Manufacturer Part Number: WM8608
• Description: The Wm8608 Comprises A High Performance Multi-channel Pwm Digital Power Amplifier Controller. Simply By Adding Appropriate Power Output Stages A Multi-channel Power Amplifier May Be Built. Six Identical Full Audio Bandwidth Channels, Plus A Reduced B
• Manufacturer: ETC-unknow

WM8608
SYNCHRONISER
Table 15 Synchroniser Specification
w
Test Conditions
AVDD, DVDD, BVDD = 3.3V, AGND, DGND, BGND = 0V, T
unless otherwise stated.
PARAMETER
Lock time
LRCLK frequency offset
LRCLK drift in Lock
The WM8608 contains a synchroniser circuit to support the synchronisation of an external LRCLK to
the local LRCLK. This mode is only supported in MPEG mode.
The specification of the synchroniser circuit is:
Table 16 Synchroniser (1)
Table 17 Synchroniser (2)
The next table illustrates recommendation for the Synchroniser loop gain G (see also Table 16) and
time-out time (Table 17) with respect to the LRCLK frequency and the resulting Synchroniser lock
time.
R32 (20h)
Synchroniser
(1)
R33 (21h)
Synchroniser
(2)
REGISTER
REGISTER
ADDRESS
ADDRESS
BIT
2:1
4:3
BIT
2:0
0
5
SYNCEN
GMIN[1:0]
GMAX[1:0]
HOLD
SYNTO[2:0]
LABEL
LABEL
SYMBOL
drift
f
A
offLRCLK
= +25
t
lock
LRCLK
o
C, f
1
10
10
0
100
DEFAULT
DEFAULT
XIN
= 27MHz, Slave Mode, fs = 48kHz, 24-bit data,
MIN
Synchroniser Enable
0: Disable
1: Enable (in MPEG mode only)
Minimum Synchroniser Gain
00: minimum gain = 2
01: minimum gain = 2
10: minimum gain = 2
11: minimum gain = 2
Maximum Synchroniser Gain
00: maximum gain = 2
01: maximum gain = 2
10: maximum gain = 2
11: maximum gain = 2
Hold Synchroniser (and SR detect)
1 : Synchroniser in hold mode
Synchroniser Gain time-out
000: 0.2 ms
001: 0.5 ms
010: 1 ms
011: 2 ms
100: 5 ms (default)
101: 10 ms
110: 20 ms
111: 50 ms
±1000
TYP
<1
DESCRIPTION
DESCRIPTION
PP Rev 1.5 March 2004
±10’000
MAX
0
1
2
3
0.2
8
10
12
14
2
6
Product Preview
ppm f
ppm/s
UNIT
Hz
s
s
24