HY27US0812B Hynix Semiconductor, HY27US0812B Datasheet
HY27US0812B
Related parts for HY27US0812B
HY27US0812B Summary of contents
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NAND FLASH HY27US(08/16)12(1/2)B This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 0.5 / Jul. 2007 512Mbit ...
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Document Title 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash Memory Revision History Revision No. 0.0 Initial Draft. 0.1 1) Correct Figure 14 & Add AC Characteristics - tRB : Last RE High to busy (at sequential read) 0.2 - ...
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FEATURES SUMMARY HIGH DENSITY NAND FLASH MEMORIES - Cost effective solutions for mass storage applications NAND INTERFACE - x8 or x16 bus width. - Multiplexed Address/ Data - Pinout compatibility for all densities SUPPLY VOLTAGE - VCC = 2.7 to ...
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SUMMARY DESCRIPTION The Hynix HY27US(08/16)12(1/2)B series is a 64Mx8bit with spare 2Mx8 bit capacity. The device is offered in 3.3V Vcc Power Supply. Their NAND cell provides the most cost-effective solution for the solid state mass storage market. The ...
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IO15 - IO8 IO7 - IO0 CLE ALE R/B Vcc Vss NC Rev 0.5 / Jul. 2007 HY27US(08/16)12(1/2)B Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash Figure1: Logic Diagram Data Input / Outputs (x16 only) Data Inputs ...
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Figure 2. 48TSOP1 Contactions, x8 and x16 Device Rev 0.5 / Jul. 2007 HY27US(08/16)12(1/2)B Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash Figure 3. 48USOP1 Contactions ...
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Figure 4. 63FBGA Contactions, x8 Device (Top view through package) Rev 0.5 / Jul. 2007 HY27US(08/16)12(1/2)B Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash 7 ...
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PIN DESCRIPTION Pin Name DATA INPUTS/OUTPUTS IO0-IO7 The IO pins allow to input command, address and data and to output data during read / program IO8-IO15(1) operations. The inputs are latched on the rising edge of Write Enable (WE). ...
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IO0 1st Cycle A0 2nd Cycle A9 3rd Cycle A17 4th Cycle A25 NOTE must be set to Low set to LOW or High by the 00h or 01h Command. IO0 1st Cycle A0 2nd ...
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CLE ALE ( NOTE: 1. With ...
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BUS OPERATION There are six standard bus operations that control the device. These are Command Input, Address Input, Data Input, Data Output, Write Protect, and Standby. Typically glitches less than Chip Enable, Write Enable and Read ...
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DEVICE OPERATION 3.1 Page Read. Three types of operations are available: random read, serial page read and sequential row read. The random read mode is enabled when the page address is changed. The 528 bytes (x8 device) or 264 ...
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Block Erase. The Erase operation is done on a block (16K Byte) basis. It consists of an Erase Setup command (60h), a Block address loading and an Erase Confirm Command (D0h). The Erase Confirm command (D0h) following the block ...
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Read Status Register. The device contains a Status Register which may be read to find out whether read, program or erase operatio is com- pleted, and whether the read, program or erase operation is completed successfully. After writing 70h ...
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OTHER FEATURES 4.1 Data Protection for Power on/off Sequence The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 2.0V(3.0V device). WP pin provides ...
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Parameter Symbol Valid Block Number NOTE: 1. The 1st block is guaranteed valid block cycles with ECC. (1bit/528bytes) Symbol Ambient Operating Temperature (Temperature Range Option Ambient Operating Temperature (Industrial Temperature Range) ...
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Rev 0.5 / Jul. 2007 HY27US(08/16)12(1/2)B Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash Figure 5: Block Diagram 17 ...
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Parameter Sequential Read Operating Current Program Erase Stand-by Current (TTL) Stand-by Current (CMOS) Input Leakage Current Output Leakage Current Input High Voltage Input Low Voltage Output High Voltage Level Output Low Voltage Leve Output Low Current (R/B) Table 9: DC ...
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Item Input / Output Capacitance Input Capacitance Table 11: Pin Capacitance (TA=25C, F=1.0MHz) Parameter Program Time Number of partial Program Cycles in the same page Block Erase Time Table 12: Program / Erase Characteristics Rev 0.5 / Jul. 2007 HY27US(08/16)12(1/2)B ...
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Parameter CLE Setup time CLE Hold time CE setup time CE hold time WE pulse width ALE setup time ALE hold time Data setup time Data hold time Write Cycle time WE High hold time Data Transfer from Cell to ...
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Pagae IO Program 0 Pass / Fail Ready/Busy 6 Ready/Busy 7 Write Protect Write Protect DEVIIDENTIFIER CYCLE 1st 2nd Part Number HY27US0812(1/2)B HY27US1612(1/2)B Rev 0.5 / Jul. 2007 512Mbit (64Mx8bit / ...
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Rev 0.5 / Jul. 2007 HY27US(08/16)12(1/2)B Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash Figure 6: Command Latch Cycle Figure 7: Address Latch Cycle 22 ...
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CE RE I/Ox R/B Notes : Transition is measured ±200mV from steady state voltage with load. This parameter is sampled and not 100% tested. Figure 9: Sequential Out Cycle after Read (CLE=L, WE=H, ALE=L) Rev 0.5 / Jul. 2007 512Mbit ...
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CLE I/O x Figure 11: Read1 Operation (Read One Page) Rev 0.5 / Jul. 2007 HY27US(08/16)12(1/2)B Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash t CLR t CLS t CLH WHR ...
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Figure 12: Read1 Operation intercepted by CE Figure 13: Read2 Operation (Sequential Row Read) Rev 0.5 / Jul. 2007 HY27US(08/16)12(1/2)B Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash 25 ...
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Figure 14: Sequential Row Read Operation Within a Block Rev 0.5 / Jul. 2007 HY27US(08/16)12(1/2)B Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash Figure 15: Page Program Operation 26 ...
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Rev 0.5 / Jul. 2007 HY27US(08/16)12(1/2)B Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash Figure 16 : Copy Back Program 27 ...
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Figure 17: Block Erase Operation (Erase One Block) CLE CE WE ALE RE 90h I/O x Read ID Command Rev 0.5 / Jul. 2007 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash tAR tREA 00h ADh Address 1 cycle Maker Code Device ...
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System Interface Using CE don’t care To simplify system interface, CE may be deasserted during data loading or sequential data-reading as shown below. So possible to connect NAND Flash to a microporcessor. The only function that was removed ...
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Figure 22: Power On and Data Protection Timing Rev 0.5 / Jul. 2007 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash Figure 21: Reset Operation VTH = 2.5 Volt for 3.3 Volt Supply devices HY27US(08/16)12(1/2)B Series 30 ...
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Figure 23: Ready/Busy Pin electrical specifications Rev 0.5 / Jul. 2007 HY27US(08/16)12(1/2)B Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash 31 ...
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Figure 25: Pointer Operations for porgramming Rev 0.5 / Jul. 2007 HY27US(08/16)12(1/2)B Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash Figure 24: Pointer operations 32 ...
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Bad Block Management Devices with Bad Blocks have the same quality level and the same AC and DC characteristics as devices where all the blocks are valid. A Bad Block does not affect the performance of valid blocks because it ...
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Write Protect Operation The Erase and Program Operations are automatically reset when WP goes Low (tWW = 100ns, min). The operations are enabled and disabled as follows (Figure 27~30) Rev 0.5 / Jul. 2007 HY27US(08/16)12(1/2)B Series 512Mbit (64Mx8bit / 32Mx16bit) ...
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Rev 0.5 / Jul. 2007 HY27US(08/16)12(1/2)B Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash Figure 29: Enable Erasing Figure 30: Disable Erasing 35 ...
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Figure 31: 48pin-TSOP1 20mm, Package Outline Symbol alpha Table 19: 48pin-TSOP1 20mm, Package Mechanical Data Rev 0.5 / Jul. 2007 HY27US(08/16)12(1/2)B Series 512Mbit (64Mx8bit / ...
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Figure 32. 48pin-USOP1 17mm, Package Outline Symbol alpha Table 20: 48pin-USOP1 17mm, Package Mechanical Data Rev 0.5 / Jul. 2007 HY27US(08/16)12(1/2)B Series 512Mbit (64Mx8bit / ...
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Figure 33. 63-ball FBGA - ball array 0.8mm pitch, Pakage Outline NOTE: Drawing is not to scale. Symbol FD1 FE FE1 SD SE Rev 0.5 ...
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MARKING INFORMATION - ...
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MARKING INFORMATION - ...