HM-6508 Intersil Corporation, HM-6508 Datasheet - Page 6

• Manufacturer Part Number: HM-6508
• Description: 1024 X 1 Cmos Ram
• Manufacturer: Intersil Corporation

In the HM-6508/883 Read Cycle, the address information is
latched into the on-chip registers on the falling edge of E
(T = 0). Minimum address setup and hold time requirements
must be met. After the required hold time, the addresses
may change state without affecting device operation. During
time (T = 1) the data output becomes enabled; however, the
data is not valid until during time (T = 2).
Timing Wavforms
TIME REFERENCE
REFERENCE
-1
0
1
2
3
4
5
TIME
W
A
D
O
E
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HIGH 2
H
H
E
L
L
(continued)
(8) TAVEL
TEHEL
-1
(7)
W
X
H
H
H
H
X
H
INPUTS
0
VALID
TELAX
A
X
V
X
X
X
X
V
FIGURE 2. WRITE CYCLE
1
HM-6508/883
(9)
(10)
TRUTH TABLE
D
X
X
X
X
X
X
X
6-74
TELWH
(14)
TELEH
W must remain high for the read cycle. After the output data
has been read, E may return high (T = 3). This will disable
the chip and force the output buffer to a high impedance
state. After the required E high time (TEHEL) the RAM is
ready for the next memory cycle (T = 4).
(6)
TWLWH
VALID DATA INPUT
OUTPUTS
TWLEH
TDVWH
Q
Z
Z
X
V
V
Z
Z
TELEL
Memory Disabled
Cycle Begins, Addresses are Latched
Output Enabled
Output Valid
Read Accomplished
Prepare for Next Cycle (Same as -1)
Cycle Ends, Next Cycle Begins (Same as 0)
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2
(13)
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3
(12)
TWHDX (11)
(8) TAVEL
TEHEL
FUNCTION
4
5
NEXT
(15)
(7)