NCP1382 ON Semiconductor, NCP1382 Datasheet
NCP1382
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NCP1382 Summary of contents
Page 1
... NCP1381, NCP1382 Low-Standby High Performance PWM Controller Housed in a SO-14 package, the NCP1381/82 includes everything needed to build rugged and efficient Quasi-Resonant (QR) Switching Power Supplies. When powered by a front-end Power Factor Correction circuitry, the NCP1381/82 automatically disconnects the PFC controller in low output loading conditions (with an adjustable level), thus improving the standby power ...
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... The IC Ground 9 DRV The Driver Output Input GTS Directly Powers the PFC Frontend Stage 12 Reference Reference Voltage NCP1381, NCP1382 TYPICAL APPLICATION EXAMPLE + NCP1381/82 V ref OPP Figure 1. Typical Application Example An internal comparator senses the signal applied to this pin (typically a portion of F signal) to detect the standby condition for GTS ...
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... ON Fault / 4 SS Timer 4 I PFlag LEB Skip/ 5 OVP OPP Offset Latchoff latch Figure 2. Internal Circuit Architecture NCP1381, NCP1382 Timer Management CC UVLO, Latchoff + - I + Timer P Flag Shot DRV Shot to Latch S Q ...
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... T Leading Edge Blanking Duration LEB S Typical Internal Soft-start Period at Startup Start S Typical Internal Soft-start period when Leaving Skip skip NCP1381, NCP1382 Rating ), Pin 9 (DRV), and Pin 11 (GTS Pin 9 (DRV), Pin 3 (DMG) and CC ), Pin 9 (DRV) and Pin 11 (GTS 0°C to +125°C, V ...
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... VBO Brown-out Level Low low I Brown-out Pin Input Bias Current BO T Temperature Shutdown, Maximum Value SD TSD Hysteresis While in Temperature Shutdown hyst NCP1381, NCP1382 = 0°C to +125° unless otherwise noted Rating between Pin 10 and Pin 11 when SW dson 3 Decreasing pin ON ...
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... Due to a novel silicon architecture, the startup current is guaranteed to be less than 15 mA maximum, helping the designer to reach a low standby power level. NCP1381, NCP1382 APPLICATION INFORMATION • Skip-cycle Capability: A continuous flow of pulses in not compatible with no-load standby power requirements ...
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... Soft-Burst Reset I Flag P Figure 4. The Timer Section Uses a Current Source to Charge Up the Capacitor NCP1381, NCP1382 As soon as V delivered on Pin 9 and the auxiliary winding grows up the V pin. Because the output voltage is below the target (the CC SMPS is starting up), the controller smoothly pushes the peak current (typical internal soft-start period) ...
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... If we want a startup below 2 s, then the charging current flowing inside the V CC NCP1381, NCP1382 above: I the above 180 mA. 3. The minimum input voltage 1.414 = 120 V. ...
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... Vds(t) has the time to go through a minimum, also called valley. Therefore, when we will finally reactivate the power MOSFET, its drain-to-source voltage will be minimum, reducing capacitive losses but also its gate-charge value, since the Miller effect gets diminished at low Vds. NCP1381, NCP1382 VCC ON VCC OFF t ON Figure 7 ...
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... D flip-flop when the 8 ms timer has not been completed, the restart is ignored until a new demagnetization signal comes in. This offers the benefit to clamp the maximum switching NCP1381, NCP1382 frequency 125 kHz. Please note that the 8 ms timer clamps ...
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... CLK R Demag 7.00 5.00 Possible Restart 3.00 1. -1.00 Figure 10. Core Reset Detection is Done Through the Monitoring of a Dedicated Auxiliary Winding NCP1381, NCP1382 Blanking - + Prioritary Reset + 45 mV One DRV Shot Fault Figure 9. Internal QR Architecture Skipping Cycle Mode The NCP1381/82 automatically skips switching cycles when the output power demand drops below a given level ...
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... Width Recurrence Figure 11. The Skip Cycle Takes Place at Low Peak Currents Which Guaranties Noise Free Operation NCP1381, NCP1382 , the skip R Figure 12. A Resistor to GND can Adjust the Skip As soon as the feedback voltage goes up again, there can be two situations as we have seen before: in normal operating conditions, e ...
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... Smooths the Current Signature Demag Restart Current Sense and Timeout Restart 8 ms Figure 14. The 8 ms Timeout Helps to Restart the Controller NCP1381, NCP1382 Figure 15. The Internal Soft-start is Activated During Each Skipped Cycles Overpower Compensation A FLYBACK converter operating in Borderline Conduction Mode (BCM) transfers energy from primary to ...
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... V , VOLTAGE (V) in Figure 18. Output Power Evolution with the Input Voltage (No Compensation) NCP1381, NCP1382 4 3 Pmax 350 400 0 Figure 17. I variable offset that will compensate the maximum output power. This would result in a variable I by the dashed line on Figure 16 ...
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... F ))) If we now plot the compensated curve, we obtain Figure 21 graph. The output power is slightly above what we NCP1381, NCP1382 0.25 = 653 mV at high line. Figure 19 shows the situation at both line levels. A possible solution lies in offsetting the current floor by the necessary value, which is, in our case, ...
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... Figure 22. Plateau Sensing Overvoltage Protection External Latchoff By lifting up Pin 5 above V (3.5 V Typ - NCP1381, latch 2.5 V Typ - NCP1382), the circuit is permanently latched. That is to say, Pin 9 goes low, the GTS pin no longer supplies the PFC and the V is clamped The latch reset CC ...
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... V This is okay. The drawback of Figure 26 is the higher forced level for lower power outputs. In our example adapter, the NCP1381, NCP1382 BCS Where FB CS setpoint. In our controller, this ratio now ...
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... Figure 27. The SW Switch is Turned Off After the Timer Confirms the Presence of a Standby During the startup sequence, the PFC is disabled (in short-circuits too) and runs as soon as the I detected, the timer runs and confirms the standby mode. When the mode is left, there is no delay and the PFC is turned-on immediately. NCP1381, NCP1382 + - Figure 28 ...
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... Pin 2 to create a brown-out detection. Please note that this technique does not use a current source for the hysteresis but rather a capacitor. It offers a way to freely select the resistive bridge impedance. NCP1381, NCP1382 BOK Figure 29. A Way to Implement a BOK Detector Flag always P The calculation procedure for R a few lines of algebra ...
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... When we reach 15 V, the logic checks whether the BOK gives the green light. If not mA. The logic arrangement is made in such a way that if the mains comes back asynchronously the upslope), we always restart at V Figure 34 and 35 confirm the good restart synchronization with the 15 V level. NCP1381, NCP1382 Bulk + 2 C ...
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... Figure 32 also includes the short-circuit latch-off phase generation. The difference between behaviors short-circuit, is the lack of latch-off phase in brown-out conditions BO, whereas it goes down and short-circuit conditions. Figure 36 shows how V short-circuit is detected conditions, the PFC is disabled as in UVLO conditions. NCP1381, NCP1382 ...
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... Plot2 V CC 25.0 15.0 5.00 -5.00 6.5 Plot3 4.5 P Reset ON 2.5 500m -1.5 14 Plot1 6.0 2.0 -2.0 41.3m The B comes back in the descent but the logic waits until the UVOL circuitry detects restart the controller. OK NCP1381, NCP1382 Bulk Voltage V CC Internal OK Signal 50.0m 70.0m TIME (s) Figure 33. 41.8m 42.4m 42.9m TIME (s) Figure 34. http://onsemi.com 90. 43.5m ...
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... UVOL circuitry detects restart the Controller. OK 8.50 18.0 6.50 14.0 4.50 10.0 2.50 6.00 500m 2.00 20.0m In short-circuit, the V drops to VCC CC latch given by the fault timer (purposely reduced on this simulation). Should a VCC be accordingly truncated. NCP1381, NCP1382 V CC 41.8m 42.4m P Reset ON 41.8m 42. 41.8m 42.4m TIME (s) Figure 35 ...
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... A shorter soft-start is also activated during the skip cycle condition to implement our soft-burst. This Soft-Skip is cancelled whenever a fault condition appears, in order not to degrade the transient behavior in case of load transients when the controller is initially in skip mode. NCP1381, NCP1382 VCC ON V VCC CC ...
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... PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com NCP1381, NCP1382 PACKAGE DIMENSIONS SOIC-14 CASE 751A-03 ISSUE ...