NCP1382 ON Semiconductor, NCP1382 Datasheet - Page 10

• Manufacturer Part Number: NCP1382
• Description: Quasi Resonant Current Mode Controller Featuring Pfc Go To Standby Function
• Manufacturer: ON Semiconductor

t
place at the switch opening: this is the leakage inductance
contribution. Unfortunately, this leakage can be detected as
a core reset event if no precaution is taken. This explains the
presence of the 3 ms blanking timer that prevents any restart
before the completion of this circuit. After leakage, the
voltage applied over the primary winding is an image of the
output voltage: this is the flyback level, or plateau level,
equal to N(V
primary and the secondary, V
the secondary diode forward drop. We are on the right
portion of Figure 8, OFF portion, the secondary current
ramping down. If we now observe the voltage on the
auxiliary winding, we will see something like what
Figure 10 shows where the plateau lasts until the core is
reset. At this reset event, a natural ringing takes place whose
amplitude depends on the ratio N and V
observes this activity and detects when the voltage drops
below ground, actually below 45 mV typically. In Figure 9,
one can see the ESD protection arrangement which
introduces a small capacitive component to Pin 3 input. This
capacitive component associated with the demagnetization
resistor can thus realize the necessary above TW delay.
of a D flip-flop. Hence, the demagnetization is edge
triggered. At the beginning of the cycle (the rising edge of
the ON time), the 8 ms timer was started. The output of this
timer goes to the D-input of the D flip-flop. Thus, if the
demagnetization comparator attempts to trip the D flip-flop
when the 8 ms timer has not been completed, the restart is
ignored until a new demagnetization signal comes in. This
offers the benefit to clamp the maximum switching
OFF
As one can see from Figure 7, a parasitic ringing takes
The comparator output now propagates to the clock input
out
+ V
f
), with N the turn ratio between the
out
the output voltage and V
out
. A comparator
NCP1381, NCP1382
http://onsemi.com
f
,
10
frequency to 8 ms or 125 kHz. Please note that the 8 ms timer
clamps t
and a new switching cycle occurs. Several events can alter
this behavior, as described below:
If everything is met, then the flip-flop output goes high
1. The converter is in light load conditions and the
2. We are skipping cycle at moderate power and the
3. The controller skips cycles at low power and the
theoretical frequency is above 125 kHz. There, the
D-input is not validated and the reset event is
ignored. The flip-flop waits for another wave to
appear. If outside of the 8 ms window, i.e. F
below 125 kHz, the event is acknowledged and a
new cycle occurs. Note that wave skipping will
always occur in the drain-source valley.
skip comparators dictates its law. In that case, if
the flip-flop is permanently reset, it naturally
ignores all demagnetization restart attempts,
provided that the drain oscillations are still there.
When the flip-flop reset is released, the controller
acknowledges the incoming demagnetization order
and drives the output high. Again, skip cycles
events always take place in the valley.
order appears in a fully damped drain-source
portion. In that case, the 8 ms timeout generator
will give the signal in place of the demagnetization
comparator. This timeout generator is reset
everytime waves appear but starts to count down
when there is no sufficient amplitude on the drain.
At the end of the 8 ms, if no wave has appeared, it
goes high, indicating that the controller is ready to
restart anytime a skip order takes place. See skip
section for more details.
ON
+ t
OFF
.
switching