NCP1382 ON Semiconductor, NCP1382 Datasheet - Page 17

• Manufacturer Part Number: NCP1382
• Description: Quasi Resonant Current Mode Controller Featuring Pfc Go To Standby Function
• Manufacturer: ON Semiconductor

is high, in low power conditions, this voltage is low.
Unfortunately, the situation complicates with QR converters
since the input voltage plays a significant role in the
feedback voltage evolution. A case can happen where the
converter is supplied by a 400 V rail and suddenly enters
standby: the PFC turns off and the bulk voltage goes low,
let's say 120 VDC (V
transfer changes, the propagation delay plays a smaller role
and the feedback voltage naturally goes up again. If a
sufficient hysteresis is not built, there are possibilities to see
hiccup on the PFC V
Therefore, hysteresis is mandatory on top of the
Go-To-Standby (GTS) detection level. For this reason it is
possible to increase the hysteresis of the ADJ_GTS
comparator due to an internal 5 mA current source that can
create an offset to the input signal if a series resistor is
inserted. The ADJ_GTS detection level is also adjustable by
tuning the portion of the external signal applied to Pin 1 (the
reference of the internal comparator is 250 mV).
we can plot these variations without compensation for a
given power, and with the offset resistor connected to the CS
pin. In the first case, the FB voltage dependency on V
be expressed by:
when the PFC is shut off. It now goes in the right direction
(FB growing up with V
cross again the upper comparison level, as it could be the
case in Figure 25. However, we must check that the offset
programmed by R
by 4, is still below our skip cycle level, otherwise the
converter will never enter skip at high line (the permanent
offset at high line will force a higher feedback):
This is okay.
lower power outputs. In our example, a 90 W adapter, the
0.147 @ 4 + 588 mV t 0.75 V
Again, to check how we manage the feedback variations,
As one can see on Figure 26, the FB level now falls down
The drawback of Figure 26 is the higher forced level for
0.35
0.25
0.15
0.3
0.2
0.1
100
Figure 25. Uncompensated FB Variations for
150
offset
in
CC
(147 mV in our example) multiplied
in
= 85 VAC). At this time, the power
200
, which is not a desirable feature.
) and this plays in our favor to not
V
in
, VOLTAGE (V)
P
out
250
= 8 W
300
350
NCP1381, NCP1382
http://onsemi.com
in
(eq. 8)
can
400
17
Where FB
setpoint. In our controller, this ratio is 4. If we now
incorporate our offset voltage generated by the R
resistor and the input voltage, the compensated FB variation
expression becomes:
with a the BO divider ratio (0.00414 in our example), gm
the transconductance slope of 80 mS and R
offset resistor.
If now plot Equation 6 and Equation 7 for a 8 W output
power, we will obtain Figures 25 and 26:
PFC will be shutdown at P
of the nominal power. If the designer needs to increase or
decrease this value, it can adjust the ADJ_GTS level, still
keeping in mind Equation 8 relationship.
capacitor of 220 nF) will be started every time the GTS
signal goes high. If at the end of the 90 ms the GTS signal
is still high, the standby is confirmed and the SW switch
between Pins 11 and 10 opens. To the opposite, when the
output power is needed, there is no delay and the SW switch
turns on immediately. Figure 27 zooms on the internal
circuitry whereas Figure 28 shows typical signal evolutions:
F B (V in ) :+ 2 @ P O @
F BComp (V in ) :+
To avoid a false tripping, the timer (90 ms with Pin 4
0.75
0.65
0.55
0.45
0.7
0.6
0.5
100
CS
@ R S @ F BCS
Figure 26. Compensated FB variations
is the ratio between the FB level and the current
150
*
@ F BCS
V in
L P
h @ V in @ N @ (V out ) V F )
2 @ P O @
200
N @ (V out ) V F ) ) V in
@ t P ] @ R S ) V in @ a @ g m @ R offset ]
V
in
out
P
, VOLTAGE (V)
out
h @ V in @ N @ (V out @ V F ) (eq. 7)
= 8 W, or a bit less than 10%
250
N @ (V out ) V F ) ) V in
= 8 W
300
offset
*
, the selected
350
V in
L P
@ t P
(eq. 6)
offset
400