LM4550B National Semiconductor Corporation, LM4550B Datasheet
LM4550B
Available stocks
Related parts for LM4550B
LM4550B Summary of contents
Page 1
... Headphone Amplifier, Sample Rate Conversion and National 3D Sound General Description The LM4550B is an audio codec for PC systems which is fully PC99 compliant and performs the analog intensive functions of the AC ’97 Rev 2.1 architecture. Using 18-bit Sigma-Delta ADCs and DACs, the LM4550B provides Dynamic Range ...
Page 2
www.national.com 2 ...
Page 3
... PHONE CD Left to Right All Analog Inputs CD Left to Right 22 -34 ≤ T −40˚C ≤ T (Note 4) A MAX 4.2V ≤ 3.0V ≤ 5V 3.3V 25˚C. The reference for LM4550B Typical Limit (Note 6) (Note 7) 4.2 5.5 3 0.013 0.02 1 0.1 1 − ...
Page 4
... High impedance AC Link outputs SDout, BitClk, SDin, Sync, Reset# only AC Link outputs Variation of BIT_CLK duty cycle from 50% SDATA_OUT to falling edge of BIT_CLK 3.3V 25˚C. The reference for Units LM4550B (Limits) Typical Limit (Note 6) (Note 7) 18 Bits (min) 20 kHz 18 ...
Page 5
... For Warm Reset Delay from end of Slot 2 to BIT_CLK, SDATA_IN low Time from minimum valid supply levels to end of Reset For ATE Test Mode For ATE Test Mode )/θ or the number given in Absolute Maximum Ratings, whichever is lower. For the LM4550B 5V 3.3V 25˚ ...
Page 6
Timing Diagrams Clocks Digital Rise and Fall www.national.com Data Delay, Setup and Hold 20123710 20123712 Power On Reset Cold Reset Warm Reset 6 20123711 Legend 20123730 20123729 20123713 20123714 ...
Page 7
... FIGURE 1. LM4550B Typical Application Circuit, Single Codec, 1 Vrms inputs APPLICATION HINTS • The LM4550B must be initialized by using RESET# to perform a Power On Reset as shown in the Power On Reset Timing Diagram • Don’t leave unused Analog inputs floating. Tie all unused inputs together and connect to Analog Ground through a capacitor (e.g. 0.1 µ ...
Page 8
www.national.com 8 ...
Page 9
... The PHONE level can be muted or adjusted from + -34 1.5 dB steps. The Stereo Mix signal feeds both the Line Out and Headphone Out analog stereo outputs and is also selectable at the Record Select Mux. Top View Order Number LM4550BVH See NS Package Number VBH48A ANALOG I/O 9 20123702 www ...
Page 10
Pin Descriptions (Continued) Name Pin Functional Description Left Stereo Channel Input This line level input (1 Vrms nominal) is selectable at the left channel of the stereo Record Select Mux for conversion by the left channel ADC. ...
Page 11
Pin Descriptions (Continued) Name Pin Functional Description Mono microphone input Either MIC1 or MIC2 can be muxed to a programmable boost amplifier with selection by the MS bit (bit D8) in the General Purpose register, 20h. The ...
Page 12
... This pin is an INPUT when the codec is configured in any of the Secondary Codec modes and would normally use the AC Link clock generated by a Primary Codec. Output from codec This is the output for AC Link Input Frames from the LM4550B codec ’97 Digital SDATA_IN 8 O Audio Controller ...
Page 13
... SYNC is also used as an active high input to perform an (asynchronous) Warm Reset. Warm Reset is used to clear a power down state on the codec AC Link interface. Cold Reset This active low signal causes a hardware reset which returns the control registers and all internal circuits to their default conditions. RESET# MUST be used to initialize the LM4550B RESET after Power On when the supplies have stabilized ...
Page 14
Pin Descriptions (Continued) Name Pin Analog supply DD1 Analog ground SS1 Analog supply 2 DD2 Analog ground 2 SS2 Digital supply DD1 ...
Page 15
Typical Performance Characteristics ADC Frequency Response Line Out Noise Floor (Analog Loopthrough) Headphone Amplifier THD+N vs Frequency (Continued) 20123719 Headphone Amplifier Noise Floor 20123718 20123727 15 DAC Frequency Response 20123720 (Analog Loopthrough) 20123726 Headphone Amplifier THD+N vs Output Power 20123728 ...
Page 16
Volume Output www.national.com Volume Input Sources ADC 16 ...
Page 17
... Functional Description GENERAL The LM4550B codec can mix, process and convert among analog (stereo and mono) and digital (AC Link format) inputs and outputs. There are four stereo and four mono analog inputs and two stereo and one mono analog outputs. A single codec supports data streaming on two input and two output channels of the AC Link digital interface simultaneously ...
Page 18
... Data Slots containing 20 bits. Input and Output Frames are aligned to the same SYNC transition. Note that the LM4550B only accepts data in eight of the twelve Data Slots and, since two channel codec only in 4 simulta- neously – 2 for control, one each for PCM data to the left and right channel DACs ...
Page 19
... Slots. With the codec in Primary mode, a controller will indicate valid data in a slot by setting the associated tag bit equal to 1. Since two channel codec the LM4550B can only receive data from four slots in a given frame and so only checks the valid-data bits for 4 slots. In Primary mode these ...
Page 20
... Comment Bits 19:0 SDATA_OUT: Slots 5, 10, 11, 12 – Reserved These slots are not used by the LM4550B and should all be stuffed with zeros by the AC ’97 Controller. FIGURE 6. AC Link Input Frame Frames are carried on the SDATA_IN signal which is an input to the AC ’97 Digital Audio Controller and an output 20 SLOTS 7 & ...
Page 21
... The LM4550B will ignore data in Output Frame slots that do not follow an Input Frame with a Slot Request. For example, if the LM4550B is expecting data at a 8000 Hz rate yet the AC ’97 Digital Audio Controller continues to send data at 48000 Hz, then only those one-in-six audio samples that follow a Slot Request will be used by the DAC ...
Page 22
... LSBs are stuffed with zeros. Bits 19:2 1:0 SDATA_IN: Slots – Reserved Slots 5 – the AC Link Input Frame are not used for data by the LM4550B and are always stuffed with zeros. 22 SLOT 2, INPUT FRAME Description Comment Data read from a codec control/status register. ...
Page 23
... RESET REGISTER (00h) Writing any value to this register causes a Register Reset which changes all registers back to their default values read is performed on this register, the LM4550B will return a value of 0D50h. This value can be interpreted in accordance with the AC ’97 specification to indicate that National 3D Sound is implemented, 18-bit data is supported for both the ADCs and DACs, and that headphone output is supported ...
Page 24
... National 3D Sound stereo enhance- ment. POWERDOWN CONTROL / STATUS REGISTER (26h) This read/write register is used both to monitor subsystem readiness and also to program the LM4550B powerdown states. The 4 LSBs indicate status and the 8 MSBs control powerdown. The 4 LSBs of this register indicate the status of the 4 audio subsections of the codec: Reference voltage, Analog mixers and amplifiers, DAC section, ADC section. When the " ...
Page 25
... EXTENDED AUDIO STATUS/CONTROL REGISTER (2Ah) This read/write register provides status and control of the variable sample rate capabilities in the LM4550B. Setting the LSB of this register to "1" enables Variable Rate Audio (VRA) mode and allows DAC and ADC sample rates to be pro- grammed via registers 2Ch and 32h respectively ...
Page 26
... LM4550B Register Map are reserved. Reserved registers will return 0000h if read. Low Power Modes The LM4550B provides 7 bits to control the powerdown state of internal analog and digital subsections and clocks. It also provides one bit intended to control an external analog power amplifier. These 8 bits (PR0 – PR6, EAPD) are the 8 www ...
Page 27
... V pin (pin 27 REF the LM4550 not required for the LM4550B. Addition of this resistor will slightly increase the temperature coefficient of the internal bandgap reference and slightly decrease the THD performance, but overall performance will still be better than the LM4550 ...
Page 28
Multiple Codecs (Continued) The Codec Identity is determined by the inverting input pins ID1#, ID0# (pins 46 and 45) and can be read as the value of the ID1, ID0 bits (D15, D14) in the Extended Audio ID register, 28h ...
Page 29
Multiple Codecs (Continued) FIGURE 9. Multiple Codecs using Extended AC Link CODEC CHAINING Using National Semiconductor’s unique feature for chaining together codecs, a multiple codec system can be built using fewer interface pins. This Chain feature allows two, three or ...
Page 30
Multiple Codecs (Continued) Test Modes AC ’97 Rev 2.1 defines two test modes: ATE test mode and Vendor test mode. Cold Reset is the only way to exit either of them. The ATE test mode is activated if SDATA_OUT is ...
Page 31
... English www.national.com Français Tel: +33 ( 8790 48-Lead , LQFP 1.4mm, JEDEC (M) Order Number LM4550BVH NS Package Number VBH48A 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system affect its safety or effectiveness ...