LM4550B National Semiconductor Corporation, LM4550B Datasheet - Page 21

• Manufacturer Part Number: LM4550B
• Description: Ac 97 Rev 2.1 Multi-channel Audio Codec With Stereo Headphone Amplifier, Sample Rate Conversion And National 3d Sound
• Manufacturer: National Semiconductor Corporation

AC Link Serial Interface Protocol
from the LM4550B codec. As shown in Figure 3, Input
Frames are constructed from thirteen time slots: one Tag
Slot followed by twelve Data Slots. The Tag Slot, Slot 0,
contains 16 bits of which 5 are used by the LM4550B. One is
used to indicate that the AC Link interface is fully operational
and the other 4 to indicate the validity of the data in the four
of the twelve following Data Slots that are used by the
LM4550B. Each Frame consists of 256 bits with each of the
twelve data slots containing 20 bits.
A new Input Frame is signaled with a low-to-high transition of
SYNC. SYNC should be clocked from the controller on a
rising edge of BIT_CLK and, as shown in Figure 6 and
Figure 7, the first tag bit in the Frame (“Codec Ready”) is
clocked from the LM4550B by the next rising edge
of BIT_CLK. The LM4550B always clocks data to SDATA_IN
on a rising edge of BIT_CLK and the controller is expected to
sample SDATA_IN on the next falling edge. The LM4550B
samples SYNC on the falling edge of BIT_CLK.
Input and Output Frames are aligned to the same SYNC
transition.
The LM4550B checks each Frame to ensure 256 bits are
received. If a new Frame is detected (a low-to-high transition
on SYNC) before 256 bits are received from an old Frame
then the new Frame is ignored i.e. no valid data is sent on
SDATA_IN until a valid new Frame is detected.
The LM4550B transmits data MSB first, in an MSB justified
format. All reserved bits and slots are stuffed with "0"s by the
LM4550B.
SDATA_IN: Slot 0 – Codec/Slot Status Bits
The first bit (bit 15, “Codec Ready”) of slot 0 in the AC Link
Input Frame indicates when the codec’s AC Link digital
interface and its status/control registers are fully operational.
The digital controller is then able to read the LSBs from the
Powerdown Control/Stat register (26h) to determine the sta-
tus of the four main analog subsections. It is important to
check the status of these subsections after Initialization,
Cold Reset or the use of the powerdown modes in order to
minimize the risk of distorting analog signals passed before
the subsections are ready.
The 4 bits 14, 13, 12 and 11 indicate that the data in slots 1,
2, 3 and 4, respectively, are valid.
(Continued)
FIGURE 7. Start of AC Link Input Frame
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21
SDATA_IN: Slot 1 – Status Address / Slot Request Bits
This slot echoes (in bits 18 – 12) the 7-bit address of the
codec control/status register received from the controller as
part of a read-request in the previous frame. If no read-
request was received, the codec stuffs these bits with zeros.
The 6 bits 11, 10, 8 – 5 are Slot Request bits that support the
Variable Rate Audio (VRA) capabilities of the LM4550B. Only
two are used simultaneously. If the codec is in Primary mode
or Secondary mode 1, then the left and right channels of the
DAC take PCM data from slots 3 and 4 in the Output Frame
respectively (see Table 1). The codec uses bits 11 and 10 to
request DAC data from these two slots. If bits 11 and 10 are
set to 0, the controller should respond with valid PCM data in
slots 3 and 4 of the next Output Frame. If bits 11 and 10 are
set to 1, the controller should not send data. Similarly, if the
codec is in Secondary mode 2, bits 7 and 6 are used to
request data from slots 7 and 8 in the Output Frame. If in
Secondary mode 3, bits 8 and 5 request data from slots 6
and 9.
The codec has full control of the slot request bits. By default,
data is requested in every frame, corresponding to a sample
rate equal to the frame rate (SYNC frequency) – 48 kHz
when XTAL_IN = 24.576 MHz. To send samples at a rate
below the frame rate, a controller should set VRA = 1 (bit 0
in the Extended Audio Control/Status register, 2Ah) and
program the desired rate into the PCM DAC Rate register,
2Ch. Both DAC channels operate at the same sample rate.
Values for common sample rates are given in the Register
Description section (Sample Rate Control Registers, 2Ch,
32h) but any rate between 4 kHz and 48 kHz (to a resolution
of 1 Hz) is supported. Slot Requests from the LM4550B are
issued completely deterministically. For example if a sample
rate of 8000 Hz is programmed into 2Ch then the LM4550B
will always issue a slot request in every sixth frame. A
frequency of 9600 Hz will result in a request every fifth frame
while a frequency of 8800 Hz will cause slot requests to be
spaced alternately five and six frames apart. This determin-
ism makes it easy to plan task scheduling on a system
controller and simplifies application software development.
The LM4550B will ignore data in Output Frame slots that do
not follow an Input Frame with a Slot Request. For example,
if the LM4550B is expecting data at a 8000 Hz rate yet the
AC ’97 Digital Audio Controller continues to send data at
48000 Hz, then only those one-in-six audio samples that
follow a Slot Request will be used by the DAC. The rest will
be discarded.
Bits 9, 4, 3, and 2 are request bits for slots not used by the
LM4550B and are stuffed with zeros. Bits 1 and 0 are
reserved and are also stuffed with zeros.
Bit
15
14
13
12
11
Codec Ready
Description
Slot 1 data
Slot 2 data
Slot 3 data
Slot 4 data
valid
valid
valid
valid
Bit
SLOT 0, INPUT FRAME
1 = AC Link Interface Ready
1 = Valid Status Address or
1 = Valid Status Data
1 = Valid PCM Data
1 = Valid PCM Data
Slot Request
(Left ADC)
(Right ADC)
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