EVX8AQ160TPY ETC-unknow, EVX8AQ160TPY Datasheet
EVX8AQ160TPY
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EVX8AQ160TPY Summary of contents
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Datasheet Main Features • Quad ADC with 8-bit Resolution – 1.25 Gsps Sampling Rate in Four-channel Mode – 2.5 Gsps Sampling Rate in Two-channel Mode – 5 Gsps Sampling Rate in One-channel Mode – Built-in four-by-four Crosspoint Switch • 2.5 ...
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EV8AQ160 Screening • Temperature Range for Packaged Device • Commercial C Grade: 0°C < T Applications • High-speed Oscilloscopes 1. Block Diagram Figure 1-1. Simplified Block Diagram Clock Buffer Selection 2.5 GHz SDA Clock Serial Peripheral Interface 2. Description The ...
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In one-channel mode, the in-phase 1.25 GHz clock is sent to ADC A while the inverted 1.25 GHz clock is sent to ADC B, the in-phase 1.25 GHz clock is delayed and the inverted 1.25 GHz ...
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EV8AQ160 Figure 2-3. Two-channel Mode Configuration (Analog Input A and Analog Input D) CLK (2.5 GHz) Figure 2-4. Two-channel Mode Configuration (Analog Input B and Analog Input C) CLK (2.5 GHz) Figure 2-5. Two-channel Mode Configuration (Analog Input B and ...
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Figure 2-6. One-channel Mode Configuration CLK (2.5 GHz) Note: For simplification purpose of the timer the temporal order of ports regarding sampling therefore samples order at output port is as follows ...
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EV8AQ160 Eight DACs for the gain and the offset controls are included in the design and are addressed through the SPI: • Offset DACs act close to the cross-point switch • Gain DACs act on the biasing of the reference ...
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Recommended Conditions of Use Table 4-1. Recommended Conditions of Use Parameter Positive supply voltage Positive digital supply voltage Positive output supply voltage Differential analog input voltage (full scale) Digital CMOS input Clock input power level Clock frequency Operating temperature ...
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EV8AQ160 Table 5-1. Electrical Characteristics (Continued) Parameter Power supply current (DMUX 1:2) Analog and SPI pads Digital Output Power supply current (full standby mode, DMUX 1:1) Analog and SPI pads Digital Output and 3-Wire serial interface Power supply current (full ...
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Table 5-1. Electrical Characteristics (Continued) Parameter Clock Inputs Source type Clock input common mode voltage (note: the clock should be AC coupled) for information only Clock input power level (low phase noise sinewave input)100Ω differential, AC coupled signal Clock input ...
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EV8AQ160 Table 5-1. Electrical Characteristics (Continued) Parameter CMOS high level output voltage (Iohc = mA) CMOS low level input current (Vinc = 0 V) CMOS high level input current (Vinc = V RESETN low level input current ...
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Table 5-1. Electrical Characteristics (Continued) Parameter INLrms Integral nonlinearity Integral nonlinearity Notes: 1. The input common mode voltage is delivered via the CMIRefAB and CMIRefCD signals for channels A and B, and C and D respectively. The minimum load allowed ...
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EV8AQ160 Table 5-2. AC Electrical Characteristics (Continued) Parameter Dynamic Performance, Four-channel Mode (Fsampling = 1.25 Gsps, –1 dBFS) for Each Channel Effective number of bits Fs = 1.25 Gsps Fin = 10 MHz Fs = 1.25 Gsps Fin = 100 ...
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Table 5-2. AC Electrical Characteristics (Continued) Parameter Dynamic Performance – One-channel Mode (Fsampling = 5 Gsps, –1 dBFS) Effective number of bits Gsps Fin = 10 MHz Gsps Fin = 100 MHz Fs = ...
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EV8AQ160 Table 5-3. Transient and Switching Performances Fc = 2.5 GHz (Continued) Parameter ADC step response rise/fall time (10 2.5 GHz Overshoot Ringback Switching Performance and Characteristics Clock frequency Sampling frequency (for each channel) Four-channel ...
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Table 5-3. Transient and Switching Performances Fc = 2.5 GHz (Continued) Parameter Output data pipeline delay Four-Channel Mode 1:1 DMUX port AH, BH, CH, DH 1:2 DMUX port AH, BH, CH, DH 1:2 DMUX port AL, BL, CL, DL Two-Channel ...
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EV8AQ160 5. TOD and TDR propagation times are defined at package input/outputs. They are given for reference only. 6. Data ready pipeline delay is given from data N clock rising edge to first change in XDR signal (with X = ...
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Figure 5-1. ADC Timing in Four-channel Mode, 1:1 DMUX Mode (for Each Channel) XAIN CLK Internal Sampling clock X0…X7 XDR Notes refers and D. 2. Not to scale. Figure 5-2. ADC Timing in Four-channel ...
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EV8AQ160 Figure 5-3. ADC Timing in Two-channel Mode, 1:1 DMUX Mode AAIN or BAIN N CAIN or DAIN M CLK Internal Sampling clocks AHD0…AHD7 BHD0…BHD7 CHD0…CHD7 DHD0…DHD7 ADR BDR CDR DDR Notes two-channel mode, the two analog inputs ...
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BAIN) and (DAIN, DAIN), in which case, the outputs corresponding to (BAI, BAIN) will be on AHD0…AHD7 and BHD0…BHD7 and the ones corresponding to (DAI, DAIN) on CHD0…CHD7 and DHD0…DHD7. 2. Not to scale. Figure 5-4. ADC Timing ...
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EV8AQ160 Notes two-channel mode, the two analog inputs can be applied on: (AAI, AAIN) and (CAI, CAIN), in which case, the outputs corresponding to (AAI, AAIN) will be on ALD0…ALD7, AHD0…AHD7 and BLD0…BLD7, BHD0…BHD7 and the ones corresponding ...
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Figure 5-5. ADC Timing in One-channel Mode, 1:1 DMUX Mode AAIN or BAIN or CAIN or DAIN CLK Internal Sampling clocks AHD0…AHD7 BHD0…BHD7 CHD0…CHD7 DHD0…DHD7 ADR BDR CDR DDR Notes one-Channel mode, the analog input can be applied ...
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EV8AQ160 Figure 5-6. ADC Timing in One-channel Mode, 1:2 DMUX Mode AAIN or BAIN or CAIN or DAIN CLK Internal Sampling clocks ALD0…ALD7 BLD0…BLD7 CLD0…CLD7 DLD0…DLD7 AHD0…AHD7 BHD0…BHD7 CHD0…CHD7 DHD0…DHD7 ADR BDR CDR DDR Notes one-channel mode, the ...
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Coding Table 5-5. ADC Coding Table Differential Analog Input +250 mV +250 mV +248.05 mV +125 mV +123.05 mV +0.976 mV –0.976 mV –123.05 mV –125 mV –248.05 mV –250 mV < –250 mV e2v semiconductors SAS 2009 Binary ...
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EV8AQ160 6. Pin Description 6.1 Pinout View (Bottom View) GND VCC BLD6 BLD7 BLOR GND AD GND VCC BLD6N BLD7N BLORN GND AC BHOR BHORN VCC GND VCC GND AB BHD7 BHD7N VCC GND VCCO VCC AA BHD6 BHD6N VCCO ...
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Pinout Table Table 6-1. Pinout Table Pin Label Pin Number Power Supplies A1, A6, A9, A12, A13, A16, A19 A24, B1, B6, B7, B8, B9, B10, B11, B14, B15, B16, B17, B18, B19, B24, C4, C7, C8, C9, C10, ...
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EV8AQ160 Table 6-1. Pinout Table (Continued) Pin Label Pin Number Digital Output Signals ALD0 M3 ALD1 L3 ALD2 K3 ALD3 J3 ALD4 H3 ALD5 G3 ALD6 A3 ALD7 A4 ALD0N M4 ALD1N L4 ALD2N K4 ALD3N J4 ALD4N H4 ALD5N ...
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Table 6-1. Pinout Table (Continued) Pin Label Pin Number BLD0 N3 BLD1 P3 BLD2 R3 BLD3 T3 BLD4 U3 BLD5 V3 BLD6 AD3 BLD7 AD4 BLD0N N4 BLD1N P4 BLD2N R4 BLD3N T4 BLD4N U4 BLD5N V4 BLD6N AC3 BLD7N ...
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EV8AQ160 Table 6-1. Pinout Table (Continued) Pin Label Pin Number CLD0 N22 CLD1 P22 CLD2 R22 CLD3 T22 CLD4 U22 CLD5 V22 CLD6 AD22 CLD7 AD21 CLD0N N21 CLD1N P21 CLD2N R21 CLD3N T21 CLD4N U21 CLD5N V21 CLD6N AC22 ...
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Table 6-1. Pinout Table (Continued) Pin Label Pin Number DLD0 M22 DLD1 L22 DLD2 K22 DLD3 J22 DLD4 H22 DLD5 G22 DLD6 A22 DLD7 A21 DLD0N M21 DLD1N L21 DLD2N K21 DLD3N J21 DLD4N H21 DLD5N G21 DLD6N B22 DLD7N ...
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EV8AQ160 Table 6-1. Pinout Table (Continued) Pin Label Pin Number Other Signals rstn AC15 scan0 AD14 scan1 AC14 scan2 AD15 SYNCN AC11 SYNCP AD11 Res50 AD18 Res62 AC18 CMIRefAB B12 CMIRefCD B13 DiodA AD7 DiodC AC7 trigp AD10 trign AC10 ...
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Characterization Results Nominal conditions (unless otherwise specified): • 3.3V • –1 dBFS analog input (Full scale Input: V • Clock input differentially driven; analog-input differentially driven • Default mode: four-channel mode ON, binary output data ...
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EV8AQ160 Figure 7-2. Crosstalk (Fc = 2.5 GHz, Channel A on Channel B) -60 -65 -70 -75 -80 -85 -90 -95 -100 -105 -110 -115 -120 0 200 Figure 7-3. Crosstalk (Fc = 2.5 GHz, Channel B on Channel C) ...
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Figure 7-4. Step Response (Fc = 2.5 GHz, DMUX 1:2 Mode, Fin = 300 MHz) 280 100% 260 240 220 90% 200 180 160 140 120 100 Figure 7-5. ENOB versus Input ...
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EV8AQ160 Figure 7-6. SNR versus Input Frequency (Fc = 2.5 GHz Figure 7-7. THD versus Input Frequency (Fc = 2.5 GHz ...
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Figure 7-8. SFDR versus Input Frequency (Fc = 2.5 GHz Figure 7-9. ENOB versus Sampling Frequency (Fin = 620 MHz ...
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EV8AQ160 Figure 7-10. SNR versus Sampling Frequency (Fin = 620 MHz Figure 7-11. THD versus Sampling Frequency (Fin = 620 MHz 0846G–BDC–11/09 ...
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Figure 7-12. SFDR versus Sampling Frequency (Fin = 620 MHz Figure 7-13. ENOB versus Power Supplies (Fc = 2.5 GHz, Fin = 100 MHz ...
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EV8AQ160 Figure 7-14. SNR versus Power Supplies (Fc = 2.5 GHz, Fin = 100 MHz Figure 7-15. THD versus Power Supplies (Fc = 2.5 GHz, Fin = 100 MHz ...
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Figure 7-16. SFDR versus Power Supplies (Fc = 2.5 GHz, Fin = 100 MHz Figure 7-17. ENOB versus Temperature (Fc = 2.5 GHz, Fin = 100 MHz ...
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EV8AQ160 Figure 7-18. SNR versus Temperature (Fc = 2.5 GHz, Fin = 100 MHz Figure 7-19. THD versus Temperature (Fc = 2.5 GHz, Fin = 100 MHz ...
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Figure 7-20. SFDR versus Temperature (Fc = 2.5 GHz, Fin = 100 MHz Figure 7-21. Dual Tone Signal Spectrum (Fc = 2.5 GHz, Fin1 = 490 MHz, Fin2 = 495 ...
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EV8AQ160 Figure 7-22. Dual Tone Signal Spectrum (Fc = 2.5 GHz, Fin1 = 490 MHz, Fin2 = 495 MHz) in Four- channel Mode 20 0 -20 -40 -60 -80 -100 -120 -140 -160 0 Figure 7-23. Dual Tone Signal Spectrum ...
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Functional Description Figure 8-1. Quad ADC Functional Diagram Table 8-1. Functions Description Name Function V 3.3V Analog power supply CCA V 1.8V Digital power supply CCD V 1.8V Output power Supply CCO GND Ground Channel A AAI, AAIN Differential ...
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EV8AQ160 Table 8-1. Functions Description (Continued) Name Function [ALD0:ALD7][ Channel A port L ALD0N:ALD7N] Differential output data [AHD0:AHD7][ Channel A port H AHD0N:AHD7N] Differential output data [BLD0:BLD7][ Channel B port L BLD0N:BLD7N] Differential output data [BHD0:BHD7] Channel B port H ...
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Examples: The SYNCN, SYNCP signal is mandatory after power up or power configuration: when switching the ADC from standby (full or partial) to normal mode. The SYNCN, SYNCP signal is mandatory after channel mode configuration: when switching the ADC from ...
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EV8AQ160 Figure 8-3. ADC Timing in 4-Channel Mode, 1:2 DMUX Mode (For Each Channel) XAIN SYNC Tsetup = 40 ps CLK Internal Sampling clock XLD0…XLD7 XHD0…XHD7 XDR Notes refers and D. This timing has ...
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The extra clock configuration allows to delay the restart of output data and data ready after SYNC. With this extra clock delay, the validity range of SYNC signal is extended. Figure 8-4. Output Data and Data Ready with Extra Delay ...
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EV8AQ160 8.2 Digital Reset (RSTN) This is a global reset for the SPI register active low. There are two ways to reset the Quad 8-bit 1.25 Gsps ADC: • By asserting low the RSTN primary pad (hardware reset) ...
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Figure 8-6. Diode Characteristics ( mA) 900 880 860 840 820 800 780 760 740 720 700 0 8.5 Test Signals The reserved signals (trigp pin AD10, trign pin AC10, tdreadyp pin AD8, tdreadyn pin AC8, tdcop pin ...
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EV8AQ160 8.6 Res50 and Res62 The Res50 and Res62 correspond to the input of internal 50Ω and 62 Ω reference resistors that are used to check the process deviation. The idea is to inject a current into pin Res50, measure ...
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Table 8-2. Registers Mapping (Continued) Address Label 0x04 SWRESET 0x05 TEST 0x06 SYNC 0x0F Channel Select Per Channel Registers (X=A/B/C/D) 0x10 Cal Ctrl X 0x11 Cal Ctrl X Mlbx 0x12 Status X 0x13 Trimmer X 0x20 Ext Offset X 0x21 ...
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EV8AQ160 8.7.2 Chip ID Register (Read Only) Table 8-3. Chip ID Register Mapping: Address 0x00 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 TYPE Table 8-4. Chip ID Register Description Bit label MINVERS <1:0> MAJVERS<1:0> BRANCH<3:0> TYPE<7:0> 8.7.3 ...
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Table 8-6. Control Register Description Bit label Value 00XX 0100 0101 0110 0111 1000 ADCMODE <3:0> 1001 1010 1011 1100 1101 1110 1111 00 01 STDBY <1:0> DMUX BDW <1:0> 10 ...
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EV8AQ160 Table 8-7. Control Register Settings (Address 0x01): Bit7 to Bit0 Description Label Four-channel mode 1.25 Gsps max. per channel Two-channel mode (channel A and channel C)2.5 Gsps max. per channel Two-channel mode (channel B and channel C)2.5 Gsps max. ...
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Table 8-8. Control Register Settings (Address 0x00): Bit15 to Bit8 Description Bit 15 Label Unused Min. bandwidth X Reduced bandwidth X Nominal bandwidth X Full bandwidth X 500 mVpp full scale X 625 mVpp full scale X Test mode OFF ...
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EV8AQ160 Table 8-9. ADCMODE and STBY Allowed Combinations (Continued) Description Label Two-channel mode, 2.5 Gsps max (Channels A and D) Standby Channel A Two-channel mode, 2.5 Gsps max (Channels A and D) Standby Channel D Two-channel mode, 2.5 Gsps max ...
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Table 8-9. ADCMODE and STBY Allowed Combinations (Continued) Description Label Common input mode (Channel B, 1.25 Gsps) Full standby Common input mode (Channel C, 1.25 Gsps) Full standby Common input mode (Channel D, 1.25 Gsps) Full standby 8.7.4 STATUS Register ...
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EV8AQ160 8.7.6 TEST Register Table 8-14. TEST Register Mapping: Address 0x05 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Notes: 1. TESTM is taken into account only if bit12 (TEST) of Control register (address 0x01 ...
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CHANNEL SELECTOR Register Table 8-17. CHANNEL SELECTOR Register Mapping: Address 0x0F Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Table 8-18. CHANNEL SELECTOR Register Description Bit label Value 000 001 010 Channel Selector <2:0> 011 100 Any ...
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EV8AQ160 Table 8-20. CAL Control Register Description (Continued) Bit label GCALCTRL X <1:0> PCALCTRL X <1:0> Notes: 1. Writing to the register will starts the corresponding operation(s). In that case, the Status/Busy bit of the mailbox (see below) is asserted ...
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GLOBAL STATUS Register (Read Only) Applies to GLOBAL STATUS registers and D according to CHANNEL SELECTOR register contents. Table 8-23. GLOBAL STATUS Register Mapping: Address 0x12 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 ...
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EV8AQ160 Table 8-26. TRIMMER Register Description Bit label TRIMMER X <3:0> Notes (121 0.006*(8*bit3 + 4*bit2 + 2*bit1 + bit0))) – the practical results (simulated) are not exactly the ones given above. ...
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Offset Registers (Read Only) Applies to offset registers and D according to CHANNEL SELECTOR register contents. Table 8-29. Offset Control Register Mapping: Address 0x21 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Unused Table ...
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EV8AQ160 8.7.17 Gain Control Registers (Read Only) Applies to gain control registers and D according to CHANNEL SELECTOR register contents. Table 8-33. Gain Control Register Mapping: Address 0x23 Bit 15 Bit 14 Bit 13 Bit 12 Bit ...
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Phase Registers (Read Only) Applies to Phase Registers and D according to CHANNEL SELECTOR register contents. Table 8-37. Phase Register Mapping: Address 0x25 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Unused Table 8-38. ...
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EV8AQ160 Table 8-42. External First level INL Register Description Bit label EXTERNAL INL1 X <7:0> Notes: 1. Actual first level INL of the selected channel is controlled by the transfer of External first level INL Regis- ter (addresses 0x30 to ...
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First Level INL Registers (Read only) Applies to first level INL registers and D according to CHANNEL SELECTOR register contents. Table 8-47. First Level INL Register Mapping: Address 0x36 to 0x38 Bit 15 Bit 14 Bit ...
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EV8AQ160 8.8 INL Calibration Procedure The calibration of the INL abides by the following rule: If there is an INL peak (+0.5 LSB) around a specific code, then this peak can be decreased by 0.15 LSB by writing a “1” ...
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Timings Figure 8-8. Register Write to a 16-bit Register CSN SCLK MOSI RW MISO Note: Last falling edge of sclk should occur only once csn is back to high level at the end of the write procedure Figure 8-9. ...
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EV8AQ160 9. Definition of Terms Table 9-1. Definition of Terms Maximum Sampling (Fs max) Frequency Minimum sampling (Fs min) frequency (BER) Bit Error Rate (FPBW) Full power input bandwidth (SSBW) Small signal input bandwidth Signal-to-noise and distortion (SINAD) ratio (SNR) ...
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Table 9-1. Definition of Terms (Continued) Maximum Sampling (Fs max) Frequency Time delay from data (TD2) ready to data (TC) Encoding clock period (TPD) Pipeline Delay (TRDR) Data ready reset delay (TR) Rise time (TF) Fall time (PSRR) Power supply ...
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EV8AQ160 10.2 Thermal Management Recommendations In still air and 25°C ambient temperature conditions, the maximum temperature for the device soldered on the evaluation board is 67.4°C. In this environment, no cooling is necessary. In the case of the need of ...
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Figure 11-2. EV8AQ160 Power Supplies Bypassing Scheme X 25 (min (min) 11.2 Analog Inputs ( INN 11.2.1 Differential Analog Input Differential mode is the recommended input scheme. A balun can be used to convert a single-ended ...
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EV8AQ160 Figure 11-4. Differential Analog Input Implementation (DC Coupled) Differential 50Ω Source V OCM (Source ICM (ADC) Notes The 50Ω terminations are implemented on-chip and can be fine tuned ...
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Digital Outputs The digital outputs are LVDS compatible. They have to be 100Ω differentially terminated. Figure 11-6. Differential Digital Outputs Terminations (100Ω LVDS) QUAD ADC Output Data Differential Output 11.5 Reset Buffer (SYNCP, SYNCN) Figure 11-7. Reset Buffer (SYNCP, ...
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EV8AQ160 12. EBGA380 Quad ADC Package Outline Figure 12-1. EBGA380 Quad ADC Package Outline 76 0846G–BDC–11/09 e2v semiconductors SAS 2009 ...
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Figure 12-2. EBGA380 Land Pattern Recommendation e2v semiconductors SAS 2009 TOP VIEW B BOTTOM VIEW ...
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... EV8AQ160 13. Ordering Information Table 13-1. Ordering Information Part Number EVX8AQ160TPY EV8AQ160CTPY EV8AQ160TPY-EB 78 0846G–BDC–11/09 Package Temperature Range EBGA380 RoHS Ambient Commercial C grade EBGA380 RoHS 0°C < T < 70°C amb EBGA380 RoHS Ambient Screening Level Comments Prototype Standard Prototype Evaluation board e2v semiconductors SAS 2009 ...
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Table of Contents Main Features............................................................................................ 1 Performance.............................................................................................. 1 Screening .................................................................................................. 2 Applications .............................................................................................. 2 1 Block Diagram .......................................................................................... 2 2 Description ............................................................................................... 2 3 Specifications .......................................................................................... 6 3.1 Absolute Maximum Ratings .................................................................................... 6 4 Recommended Conditions of Use ......................................................... 7 ...
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EV8AQ160 10 Thermal and Moisture Characteristics ................................................ 71 10.1 Thermal Characteristics ...................................................................................... 71 10.2 Thermal Management Recommendations .......................................................... 72 10.3 Moisture Characteristics ...................................................................................... 72 11 Quad ADC Application Information ..................................................... 72 11.1 Bypassing, Decoupling and Grounding ............................................................... 72 11.2 Analog ...
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How to reach us Home page: www.e2v.com Sales offices: Europe Regional sales office e2v ltd 106 Waterhouse Lane Chelmsford Essex CM1 2QU England Tel: +44 (0)1245 493493 Fax: +44 (0)1245 492492 mailto: enquiries@e2v.com e2v sas 16 Burospace F-91572 Bièvres Cedex ...
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EV8AQ160 0846G–BDC–11/09 e2v semiconductors SAS 2009 ...