EVX8AQ160TPY ETC-unknow, EVX8AQ160TPY Datasheet - Page 62

• Manufacturer Part Number: EVX8AQ160TPY
• Description: Adc Quad 1.25gsps 8-bit Lvds 380-pin Ebga
• Manufacturer: ETC-unknow

8.7.14
Table 8-27.
62
Bit 15
EV8AQ160
0846G–BDC–11/09
External Offset Registers
Bit 14
External Offset Control Register Mapping: Address 0x20
Table 8-26.
Notes:
Applies to External Offset Registers A, B, C and D according to CHANNEL SELECTOR register
contents.
Table 8-28.
Notes:
Bit 13
Bit label
TRIMMER X
<3:0>
Bit label
EXTERNAL
OFFSET X
<7:0>
1. R = 1 + (121*k / (2 + 0.006*(8*bit3 + 4*bit2 + 2*bit1 + bit0))) – the practical results (simulated) are not
2. Please refer to
1. Offset variation range: ~± 50 mV, 256 steps (1 step ~0.4 mV ~0.2 LSB).
2. Current offset of the selected channel is controlled by the External Offset Control Register but is
Bit 12
Unused
exactly the ones given above.
updated only upon request placed through the SPI in the CAL control register of the selected channel.
TRIMMER Register Description
External Offset Control Register Description
Bit 11
Value
0000
0001
0010
0011
0100
0101
0110
1000
1000
1001
1010
1011
1100
1101
1110
1111
Value
0x00
0x7F
0x80
0xFF
Section 8.6
Bit 10
Bit 9
for more information.
Description
+11.71Ω
+9.95Ω
+8.29Ω
+6.71Ω
+5.23Ω
+3.82Ω
+2.48Ω
+1.21Ω
0.00Ω
–1.15Ω
–2.25Ω
–3.30Ω
–4.31Ω
–5.27Ω
–6.18Ω
–7.07Ω
Description
Maximum negative offset applied
Minimum negative offset applied
Minimum positive offset applied
Maximum positive offset applied
Bit 8
Bit 7
Bit 6
EXTERNAL OFFSET X <7:0>
Bit 5
Bit 4
Bit 3
e2v semiconductors SAS 2009
Bit 2
Default Setting
1000
+0Ω
Default Setting
0x800 LSB
Offset
(1)
Bit 1
Bit 0