EVX8AQ160TPY ETC-unknow, EVX8AQ160TPY Datasheet - Page 58

• Manufacturer Part Number: EVX8AQ160TPY
• Description: Adc Quad 1.25gsps 8-bit Lvds 380-pin Ebga
• Manufacturer: ETC-unknow

8.7.6
Table 8-14.
Notes:
8.7.7
58
Bit 15
EV8AQ160
1. TESTM is taken into account only if bit12 (TEST) of Control register (address 0x01) is at 1.
2. It is mandatory to apply a SYNC, SYNCN signal to the ADC whenever the test mode is activated or deactivated. There is no
Bit 14
0846G–BDC–11/09
TEST Register
SYNC Register
need to perform a SYNCP, SYNCN when the ADC returns to normal running mode.
TEST Register Mapping: Address 0x05
Bit 13
Table 8-15.
Table 8-16.
Bit label
TESTM
Bit label
SYNC<3:0>
Bit 12
Bit 11
SYNC Register Description
Bit 10
Value
0
1
Value
0000
0001
...
1111
Unused
Bit 9
Bit 8
Bit 7
Description
Increasing simultaneous ramp
Flashing 1 (1 FF pattern every ten
00 patterns) on each ADC
Description
0 extra clock cycle before starting up
1 extra clock cycle before starting up
15 extra clock cycles before starting up
Bit 6
Bit 5
Bit 4
Bit 3
0
Increasing ramp
Default Setting
e2v semiconductors SAS 2009
Bit 2
RESERVED
Default Setting
00000
Clock cycle
Bit 1
Bit 0
TEST M