LMX2487 National Semiconductor Corporation, LMX2487 Datasheet
LMX2487
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LMX2487 Summary of contents
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... The LMX2487 offers fine frequency resolution, low spurs, fast programming speed, and a single word write to change the frequency. This makes it ideal for direct digital modula- tion applications, where the N counter is directly modulated with information. The LMX2487 is available lead 4.0 X 4.0 X 0.8 mm LLP package. Applications n Cellular phones and base stations ...
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Connection Diagram Pin Descriptions Pin # Pin I/O Name 0 GND - Ground Substrate. This is on the bottom of the package and must be grounded. 1 CPoutRF O RF PLL charge pump output. 2 GND - RF PLL analog ...
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... Power Supply Current Synthesizer Power Supply Current, I TOTAL CC Entire Synthesizer I PD Power Down Current CC RF SYNTHESIZER PARAMETERS Operating f LMX2487 FinRF Frequency p Input Sensitivity FinRF Phase Detector f Frequency COMP (Note 3) RF Charge Pump I SRCE Source Current CPoutRF (Note 4) (Notes 1, 2) ...
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Electrical Characteristics Symbol Parameter RF SYNTHESIZER PARAMETERS RF Charge Pump Sink I SINK Current CPoutRF (Note 4) RF Charge Pump I TRI TRI-STATE Current CPoutRF Magnitude Magnitude %MIS | Sink vs. CP Source CPoutRF Mismatch ...
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Electrical Characteristics Symbol Parameter PHASE NOISE RF Synthesizer L RF Normalized Phase Noise F1Hz Contribution(Note 6) IF Synthesizer L IF Normalized Phase Noise F1Hz Contribution DIGITAL INTERFACE (DATA, CLK, LE, ENOSC, CE, Ftest/LD, FLoutRF) V High-Level Input Voltage IH V ...
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Typical Performance Characteristics : Sensitivity www.national.com (Note 7) RF PLL Fin Sensitivity T = 25˚C, RF_P = PLL Fin Sensitivity V = 3.0 V, RF_P = 20154745 20154746 ...
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Typical Performance Characteristics : Sensitivity (Note 7) IF PLL Fin Sensitivity T = 25˚C, IF_P = PLL Fin Sensitivity V = 3.0 V, IF_P = (Continued) 20154747 20154748 www.national.com ...
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Typical Performance Characteristics : Sensitivity www.national.com (Note 7) OSCin Sensitivity T = 25˚C, OSC_2X = 0 A OSCin Sensitivity V = 3.0 V, OSC_2X = (Continued) 20154749 20154756 ...
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Typical Performance Characteristics : Sensitivity (Note 7) OSCin Sensitivity T = 25˚C, OSC_2X =1 A OSCin Sensitivity V = 3.0 V, OSC_2X = (Continued) 20154773 20154774 www.national.com ...
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Typical Performance Characteristic : FinRF Input Impedance Frequency (MHz) 3000 3200 3400 3600 3800 4000 4250 4500 4750 5000 5250 5500 5750 6000 6250 6500 6750 7000 www.national.com 20154768 FinRF Input Impedance Real (Ohms ...
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Typical Performance Characteristic : FinIF Input Impedance Frequency (MHz) 100 150 200 250 300 400 500 600 700 800 900 1000 1200 1400 1600 1800 2000 2200 2300 2400 2600 2800 3000 FinIF Input Impedance Real (Ohms) 508 456 420 ...
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Typical Performance Characteristic : OSCin Input Impedance Frequency (MHz) Real 5 1730 10 846 20 466 30 351 40 316 50 278 60 261 70 252 80 239 90 234 100 230 110 225 120 219 130 214 140 208 ...
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Typical Performance Characteristics : Currents (Note 7) Power Supply Current CE = High RF PLL Charge Pump Current V = 3.0 Volts CC 13 20154759 20154767 www.national.com ...
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Typical Performance Characteristics : Currents www.national.com (Note 7) IF PLL Charge Pump Current V = 3.0 Volts CC Charge Pump Leakage RF PLL V = 3.0 Volts CC 14 (Continued) 20154765 20154764 ...
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Typical Performance Characteristics : Currents Note 7: Typical performance characteristics do not imply any sort of guarantee. Guaranteed specifications are in the electrical characteristics section. (Note 7) Charge Pump Leakage IF PLL V = 3.0 Volts CC 15 (Continued) 20154763 ...
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Bench Test Setups Charge Pump Current Measurement Procedure The above block diagram shows the test procedure for testing the RF and IF charge pumps. These tests include absolute current level, mismatch, and leakage measurement. In order to measure the charge ...
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Bench Test Setups (Continued) Charge Pump Current Specification Definitions I1 = Charge Pump Sink Current at V CPout I2 = Charge Pump Sink Current at V CPout I3 = Charge Pump Sink Current at V CPout I4 = Charge Pump ...
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... The expected frequency at the Ftest/LD pin should be the signal generator frequency divided by twice the corresponding counter value. The factor of two comes in because the LMX2487 has a flip-flop which divides this frequency by two to make the duty cycle 50% in order to make it easier to read with the frequency counter. The frequency counter input impedance should be set to high impedance ...
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... Input Impedance Measurement Procedure The above block diagram shows the test setup used for measuring the input impedance for the LMX2487. The DC blocking capacitor used between the input SMA connector and the pin being measured must be changed to a zero Ohm resistor. This procedure applies to the FinRF, FinIF, and OSCin pins ...
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... The small capacitor should be placed as close as possible to the pin. The power down state of the LMX2487 is controlled by many factors. The one factor that overrides all other factors is the CE pin. If this pin is low, the part will be powered down. ...
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Functional Description (Continued) ATPU Bit Enabled + Write Pin RF_PD N Counter Low X X High X Yes High 0 No High 1 No 1.7 DIGITAL LOCK DETECT OPERATION The RF PLL digital lock detect circuitry compares ...
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... Functional Description (Continued) 1.8 CYCLE SLIP REDUCTION AND FASTLOCK The LMX2487 offers both cycle slip reduction (CSR) and Fastlock with timeout counter support. This means that it requires no additional programming overhead to use them generally recommended that the charge pump current in the steady state less in order to use cycle slip reduction, and 4X or less in steady state in order to use Fastlock ...
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... Capacitor Dielectric Considerations for Lock Time The LMX2487 has a high fractional modulus and high charge pump gain for the lowest possible phase noise. One consideration is that the reduced N value and higher charge pump may cause the capacitors in the loop filter to become larger in value ...
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... Control Register Content Map Because the LMX2487 registers are complicated, they are organized into two groups, basic and advanced. The first four registers are basic registers that contain critical information necessary for the PLL to achieve lock. The last 5 registers are for features that optimize spur, phase noise, and lock time performance ...
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25 www.national.com ...
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Programming Description 2.1 R0 REGISTER Note that this register has only one control bit, so the N counter value to be changed with a single write statement to the PLL. REGISTER RF_N[10:0] 2.1.1 RF_FN[11:0] ...
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Programming Description 2.2 R1 REGISTER REGISTER RF_PD RF_P 2.2.1 RF_FD[11: PLL Fractional Denominator The function of these bits are described in section 2.6.2. 2.2.2 RF_R [5: Divider Value The RF ...
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Programming Description 2.3 R2 REGISTER REGISTER IF_PD 2.3.1 IF_N[18: Divider Value IF_N Counter Programming with the 8/9 Prescaler (IF_P=0) N Value ≤23 N values less than or equal to 23 are prohibited ...
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Programming Description 2.4 R3 REGISTER REGISTER ACCESS[3:0] RF_CPG[3:0] 2.4.1 IF_R[11: Divider Value For the IF R divider, the R value is determined by the IF_R[11:0] bits in the R3 register. The ...
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Programming Description This corresponds to the following bit settings. Register Bit Location Bit Name R4[23] ATPU R4[17:16] DITH R4[15:16] FM R4[23] OSC_2X R4 R4[23] OSC_OUT R4[23] IF_CPP R4[23] RF_CPP R4[23] IF_P R4[7:4] MUX R5[23:14] RF_FD[21:12] R5 R5[13:4] RF_FN[21:12] R6[23:22] CSR ...
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Programming Description 2.5 R4 REGISTER This register controls the conditions for the RF PLL in Fastlock. REGISTER ATPU 2.5.1 MUX[3:0] Frequency Out & Lock ...
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Programming Description 2.5.6 OSC2X -- Oscillator Doubler Enable When this bit is set to 0, the oscillator doubler is disabled and the TCXO frequency presented to the IF R and RF R counters is equal to that of the input ...
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Programming Description 2.6 R5 REGISTER REGISTER RF_FD[21:12] 2.6.1 Fractional Numerator Determination { RF_FN[21:12], RF_FN[11:0], ACCESS[ the case that the ACCESS[1] bit is 0, then the part operates in 12-bit fractional mode, and ...
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Programming Description 2.7 R6 REGISTER REGISTER CSR[1:0] RF_CPF[3:0] 2.7.1 RF_TOC -- RF Time Out Counter and Control for FLoutRF Pin The RF_TOC[13:0] word controls the operation of the RF Fastlock circuitry as well as ...
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Programming Description 2.7.3 CSR[1: Cycle Slip Reduction CSR controls the operation of the Cycle Slip Reduction Circuit. This circuit can be used to reduce the occurrence of phase detector cycle slips. Note that the Fastlock charge pump current, ...
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Programming Description 2.8 R7 REGISTER REGISTER 2.8.1 DIV4 -- RF Digital Lock Detect Divide By 4 Because the digital lock detect function is ...
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... Français Tel: +33 ( 8790 Plastic Quad LLP (SQ), Bottom View Order Number LMX2487SQXfor 4500 Unit Reel Order Number LMX2487SQ for 1000 Unit Reel NS Package Number SQA24A 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system affect its safety or effectiveness ...