LMX2487 National Semiconductor Corporation, LMX2487 Datasheet - Page 31

• Manufacturer Part Number: LMX2487
• Description: 3.0 Ghz - 6.0 Ghz High Performance Delta-sigma Low Power Dual Pllatinum? Frequency Synthesizers With 3.0 Ghz Integer Pll
• Manufacturer: National Semiconductor Corporation

REGISTER
Programming Description
2.5 R4 REGISTER
This register controls the conditions for the RF PLL in Fastlock.
2.5.1 MUX[3:0] Frequency Out & Lock Detect MUX
These bits determine the output state of the Ftest/LD pin.
2.5.2 IF_P -- IF Prescaler
When this bit is set to 0, the 8/9 prescaler is used. Otherwise the 16/17 prescaler is used.
2.5.3 RF_CPP -- RF PLL Charge Pump Polarity
2.5.4 IF_CPP -- IF PLL Charge Pump Polarity
For a positive phase detector polarity, which is normally the case, set this bit to 1. Otherwise set this bit for a negative phase
detector polarity.
2.5.5 OSC_OUT Oscillator Output Buffer Enable
R4
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
ATPU
23
IF_P
0
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
MUX[3:0]
22 21 20 19 18 17 16 15 14 13
0
OSC_OUT
RF_CPP
IF_CPP
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DITH
[1:0]
(Continued)
IF Prescaler
High Impedance
[1:0]
16/17
FM
Output Type
Open Drain
Open Drain
Open Drain
8/9
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
DATA[19:0]
0
31
OSC_
2X
12
OSC_
OUT
11
Buffered output of OSCin pin
General purpose output, Logical “High” State
RF Charge Pump Polarity
General purpose output, Logical “Low” State
Disabled (High Impedance)
IF Charge Pump Polarity
CPP
IF_
10
Positive (Default)
OSCout Pin
RF & IF Analog Lock Detect
RF & IF Analog Lock Detect
RF & IF Digital Lock Detect
CPP
RF_
Negative
Negative
RF R Divider divided by 2
RF N Divider divided by 2
Positive
IF R Divider divided by 2
IF N Divider divided by 2
9
RF Analog Lock Detect
RF Analog Lock Detect
RF Digital Lock Detect
IF Analog Lock Detect
IF Analog Lock Detect
IF Digital Lock Detect
Output Description
Maximum Frequency
IF_P
8
Disabled
800 MHz
800 MHz
7 6 5 4
MUX
[3:0]
C3 C2 C1 C0
3
1
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2
0
1
0
0
1