HT45R37V Holtek Semiconductor Inc., HT45R37V Datasheet
HT45R37V
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HT45R37V Summary of contents
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... General Description TM The HT45R37V is a TinyPower C Type 8-bit high performance RISC architecture microcontroller designed especially for VFD applications C type of MCU, the device can interface to 9 external type sensors and convert their values to a frequency value for processing ...
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... Block Diagram Pin Assignment Rev. 1.00 2 HT45R37V October 20, 2009 ...
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... CMOS outputs or Schmitt Trigger inputs. A pull high resistor can be connected to each pin using the PCPU register. Configura- tion options determine if the pins are to be used as oscillator pins or I/O pins. If configuration options select oscillator pins, the pins are connected to a 32768Hz crystal oscillator. 3 HT45R37V October 20, 2009 ...
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... High voltage grid/segment output for VFD panel Positive power supply/analog positive power supply. Negative power supply, ground/analog negative power supply, ground +6.0V Storage Temperature ............................ 125 C SS +0.3V Operating Temperature........................... Total ................................................................80mA OL Total Power Dissipation .....................................500mW 4 HT45R37V October 20, 2009 ...
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... No load =2MHz 5V SYS SLOW 3V No load =4MHz SYS SLOW load, WDT off load, system HALT, WD off load, system HALT, WDT HT45R37V Ta=25 C Typ. Max. Unit 2.2 5.5 V 3.0 5.5 V 4.5 5.5 V 2.7 5.5 V 170 250 A 380 700 A 240 360 A 490 800 ...
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... REF VDD t =0 =5V REF VDD t =0 For =(V +0.1V) to 24V, IN OUT I =1mA OUT I =100 A to 20mA, OUT C =10pF OUT 6 HT45R37V Typ. Max. Unit 0. 0. 2.1 2.22 V 3.15 3.32 V 4.2 4.42 V 2.2 2.32 V 3.3 3 ...
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... 24V 18V 24V 18V 24V 18V 24V , I tests. DD STB 7 HT45R37V Typ. Max. Unit 110 A 90 135 A 70 110 A 90 135 A 100 150 A 120 180 A 80 120 A 100 150 A 70 105 ...
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... CC V =15V CC V =15V CC V =15V CC V =15V CC V =15V CC V =15V CC V =15V CC V =15V CC V =15V CC 8 HT45R37V Ta=25 C Typ. Max. Unit 4000 kHz 8000 kHz 12000 kHz 4000 +2% kHz 8000 +2% kHz 12000 +2% kHz 32768 Hz 4000 +2% kHz 32768 Hz 4000 kHz ...
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... A.C. Waveforms Data Propagation Delays, Setup and Hold Times Strobe Propagation Delays, Setup and Hold Times Rev. 1.00 9 HT45R37V October 20, 2009 ...
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... VDD Start Voltage to Ensure V POR Power-on Reset VDD raising rate to Ensure RR VDD Power-on Reset Minimum Time for VDD Stays at t POR V to Ensure Power-on Reset POR Rev. 1.00 Test Conditions Min. V Conditions DD 0.035 1 10 HT45R37V Typ. Max. Unit 100 mV V/ms ms October 20, 2009 ...
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... The requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. System Clocking and Pipelining Instruction Fetching 11 HT45R37V October 20, 2009 ...
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... Program Counter + # S10 Program Counter @7~@0: PCL bits S11~S0: Stack register bits 12 HT45R37V ...
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... Location 00CH This internal vector is used by the Timer/Event Coun- ter Timer/Event Counter 0 overflow occurs, the program will jump to this location and begin execution if the timer/event counter interrupt is enabled and the stack is not full. 13 HT45R37V October 20, 2009 ...
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... Any unused bits in this transferred higher order byte will be read The following diagram illustrates the addressing/data flow of the look-up table: Table Location Bits PC8 @ Table Location 14 HT45R37V October 20, 2009 ...
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... However, in situations where simultaneous use cannot be avoided, the inter- rupts should be disabled prior to the execution of any main routine table-read instructions. Note that all table related instructions require two instruction cycles to complete their operation. 15 HT45R37V October 20, 2009 ...
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... Rev. 1.00 which are located under the relevant Special Function Register section. Note that for locations that are unused, any read instruction to these addresses will return the value 00H . Special Purpose Data Memory 16 HT45R37V October 20, 2009 ...
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... Indirect Addressing Regis- ters is carried out, the actual address that the microcontroller is directed to, is the address specified by the related Memory Pointer. The following example shows how to clear a section of four RAM locations already defined as locations adres1 to adres4. 17 HT45R37V October 20, 2009 ...
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... OV is cleared. PDF is cleared by a system power-up or executing the CLR WDT instruction. PDF is set by executing the HALT instruction cleared by a system power-up or executing the CLR WDT or HALT instruction set by a WDT time-out. Status Register 18 HT45R37V October 20, 2009 ...
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... Pull-High Resistors - PAPU, PBPU, PCPU, PDPU All I/O pins on Ports PA, PB, PC and PD, if setup as in- puts, can be connected to an internal pull-high resistor. The pins which require a pull-high resistor to be con- nected are selected using these registers. 19 HT45R37V October 20, 2009 ...
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... Note that the original I/O function will remain even if the pin is setup to be used as an external timer input. 20 HT45R37V October 20, 2009 ...
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... PA0~PA3 Open Drain Control - MISC Rev. 1.00 Generic Input/Output Structure A/D Input/Output Structure 21 HT45R37V October 20, 2009 ...
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... Port A has the additional capability of providing wake-up functions. When the device is in the Power Down Mode, various methods are available to wake the device up. One of these is a high to low transition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this function. 22 HT45R37V October 20, 2009 ...
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... Use the STROBE line to latch the shift-register data to the VFD0~VFD23 outputs. When the STROBE line is high, the shift register data will be latched to the VFD lines. Note that the STROBE line is level and not edge triggered. VFD Driver 23 HT45R37V October 20, 2009 ...
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... VFD display operation advised that the configuration options select pull-high resistors to be connected to these lines to keep the lines at a fixed high level when power is initially applied and until the lines can be setup as outputs. 24 HT45R37V October 20, 2009 ...
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... Control Register Operating Mode Select Bits for the Timer Mode In this mode the internal clock used as the inter- SYS nal clock for the Timer/Event Counter. However, the clock source for the 8-bit timer is further divided by SYS 25 HT45R37V Bit7 Bit6 1 0 October 20, 2009 ...
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... Timer/Event Counter Structure (n=0, 1) Timer/Event Counter Control Register - TMRnC Rev. 1.00 ¸ 26 HT45R37V October 20, 2009 ...
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... Timer/Event Counter will start counting until the external timer pin returns to its original high level. At this point the enable bit will be automatically reset to zero and the Timer Mode Timing Chart Event Counter Mode Timing Chart 27 HT45R37V Bit7 Bit6 used as the inter- SYS ...
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... The timer will begin to count-up from this preload register value until full, at which point an overflow signal is generated, causing the PFD output to change state. The timer will then be auto- matically reloaded with the preload register value and continue counting-up. 28 HT45R37V October 20, 2009 ...
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... Power-down condition. To prevent such a wake-up from occurring, the timer interrupt re- quest flag should first be set high before issuing the HALT instruction to enter the Power Down Mode. 29 HT45R37V October 20, 2009 ...
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... TMRAL and TMRBL, only writes the data into a low byte buffer. However writing to the high byte registers, TMRAH and TMRBH, will write both the high byte values and the low byte buffer values directly into the Timer A and Timer B simultaneously. 30 HT45R37V October 20, 2009 ...
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... Rev. 1.00 C Converter RCOCCR Register RCOCR Register 31 HT45R37V October 20, 2009 ...
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... Similarly if the configuration options have selected PD0 to be normal I/O pin, then the corre- sponding bits in the ASCR2 register, bit 4, must be cleared to zero to disable the RC8 pull-low resistor. the ASCR2 register bit7~bit5 must to be cleared to zero by applica- tion program. 32 HT45R37V October 20, 2009 ...
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... Rev. 1.00 ASCR0 Register ASCR1 Register ASCR2 Register 33 HT45R37V October 20, 2009 ...
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... Timer A clock source=f mov RCOCCR, a p10: clr wdt snz mfic0.5 ; Polling External RC Oscillation Converter interrupt request flag jmp p10 clr mfic0.5 ; Clear External RC Oscillation Converter interrupt request flag ; Program continue Rev. 1.00 /4 and timer on SYS 34 HT45R37V October 20, 2009 ...
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... PWM function, but if the corre- sponding bit in the PDC control register is high to config- Duty ure the pin as an input, then the pin can still function as a normal input line, with pull-high resistor selections. 35 HT45R37V AC (0~15) DC (Duty Cycle) DC 256 ...
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... PWM0L register value clr pdc.0 ; setup pin PD0 as an output set pwm0en ; set the PWM0 enable bit set pd.0 ; Enable the PWM0 output : : : : clr pd.0 ; PWM0 output disabled Rev. 1.00 PD0 will remain low 8+4 PWM Mode PWM Register Pairs 36 HT45R37V October 20, 2009 ...
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... The START bit in the register is used to start and reset the A/D converter. When the microcontroller sets this bit from low to high and then low again, an analog to digital ¸ A/D Converter Structure 37 HT45R37V Bit Bit Bit Bit Bit Bit 5 ...
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... Refer to the following table for exam- ples, where values marked with an asterisk * show where, depending upon the device, special care must be taken, as the values may be less than the specified minimum A/D Clock Period. 38 HT45R37V A/D Off On Off , is 0.5 s, care must be AD ...
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... Select which pins on Port B are to be used as A/D in- puts and configure them as A/D input pins by correctly programming the PCR2~PCR0 bits in the ADCR reg- ister. Note that this step can be combined with Step 2 into a single ADCR register programming operation. 39 HT45R37V ADCS2, ADCS1, ADCS0=011 Undefined Undefined Undefined ...
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... The following two programming examples illustrate how to setup and implement an A/D conversion. In the first example, the method of polling the EOCB bit in the ADCR register is used to detect when the conversion cycle is complete, whereas in the second example, the A/D interrupt is used to determine when the conversion is complete. 40 HT45R37V AD October 20, 2009 ...
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... STATUS from user defined memory ; restore ACC from user defined memory ; clear ADC interrupt flag 41 HT45R37V October 20, 2009 ...
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... The Master also controls the clock signal. As the device only contains a single SCS pin only one slave device can be utilised. The SPI function in this device offers the following fea- tures: Full duplex synchronous data transfer Both Master and Slave modes 42 HT45R37V October 20, 2009 ...
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... I C interface. Slave - SIMEN=1 CSEN=1 CSEN=1 CSEN CKPOL CKPOL=1 SPI Interface Pin Status SPI Block Diagram 43 HT45R37V Function SIM interface enable/disable Enable/Disable Enable/Disable CSEN=1 SCS=0 SCS October 20, 2009 ...
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... SPI/I Rev. 1. Control Register - SIMCTL0 2 C Control Register - SIMCTL1 I SPI Control Register - SIMCTL2 44 HT45R37V October 20, 2009 ...
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... HT45R37V SPI function, SPI Master/Slave Clock Control and I2C Enable SPI Master SYS SPI Master, f /16 SYS SPI Master, f /64 SYS SPI Master, f SUB SPI Master Timer/Event Counter 0 output/2 SPI Slave ...
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... Rev. 1.00 SPI Master Mode Timing SPI Slave Mode Timing (CKEG=0) SPI Slave Mode Timing (CKEG=1) 46 HT45R37V October 20, 2009 ...
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... Rev. 1.00 SPI Transfer Control Flowchart 47 HT45R37V October 20, 2009 ...
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... Both master and slave can transmit and receive data, however the master de- vice that has overall control of the bus. For these de- vices, which only operates in slave mode, there are two 48 HT45R37V 2 C bus is identified by a October 20, 2009 ...
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... C bus must sending out data until the RXAK bit is set high. When this occurs, the device will release the SDA line to al- low the master to send a STOP signal to release the bus. 49 HT45R37V 2 C interface. The SIMCTL0 2 C interface 2 C interface to ...
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... Step 1 Write the slave address of the microcontroller to the I bus address register SIMAR. C Slave Address Register - SIMAR 50 HT45R37V 2 C bus, sends out an address bus requires four separate 2 C bus, all de- ...
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... I Rev. 1.00 C Communication Timing Diagram Bus ISR Flow Chart 51 HT45R37V October 20, 2009 ...
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... RXAK bit in the SIMCTL1 register to determine send another data byte, if not then it will release the SDA line and await the receipt of a STOP signal from the master bus as 52 HT45R37V 2 C bus, whose own internal 2 C bus. The corresponding data October 20, 2009 ...
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... BZ buzzer pin PA1. PA Data Register PA Data Register PA0 PA1 Buzzer Function 53 HT45R37V Output Function PA0=BZ PA1=BZ PA0= 0 PA1= 0 PA0=BZ PA1=input line PA0= 0 PA1=input line PA0=input line PA1=D PA0=input line PA0=input line October 20, 2009 ...
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... Buzzer Output Pin Control 54 HT45R37V October 20, 2009 ...
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... INT0 or INT1 pin. The external interrupt pins are pin-shared with the I/O pins PA6 and PA7 and can only be configured as external interrupt pins if their corresponding external interrupt enable bit in the INTC0 register has been set. 55 HT45R37V Priority Vector 1 04H 2 ...
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... Rev. 1.00 Interrupt Control Register INTC0 Interrupt Control Register INTC1 56 HT45R37V October 20, 2009 ...
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... Interrupt Control Register - MFIC0 Interrupt Control Register - MFIC1 Rev. 1.00 57 HT45R37V October 20, 2009 ...
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... Timer/Event Counter exter- nal input pins. Individual external interrupt or Timer/Event Counter pins cannot be selected to have a filter on/off function. 58 HT45R37V October 20, 2009 ...
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... C address match occurs, a subroutine call to the Multi-function Interrupt 0 vector at location 14H, will take place. When the interrupt is serviced, the Multi-function Interrupt 0 request flag, MF0F, will be automatically re- set and the EMI bit will be automatically cleared to dis- 59 HT45R37V 2 C interface interface or October 20, 2009 ...
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... When the interrupt is enabled, the stack is not full and the Time Base overflows, a subroutine call to the Multi-function Interrupt 1 vector at location18H, will take place. When the Time Base Interrupt is serviced, the EMI bit will be cleared to disable other interrupts, how- RTC Interrupt Time Base Interrupt 60 HT45R37V . This ...
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... Power Down Mode. Only the Program Counter is pushed onto the stack. If the contents of the status or other registers are altered by the interrupt service program, which may corrupt the desired control sequence, then the contents should be saved in advance. 61 HT45R37V October 20, 2009 ...
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... It is recommended that this component is added for added ESD protection ** It is recommended that this component is added in environments where power line noise is significant External RES Circuit More information regarding external reset circuits is located in Application Note HA0075E on the Holtek website. 62 HT45R37V October 20, 2009 ...
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... All interrupts will be disabled Clear after reset, WDT begins WDT counting Timer/Event Counter Timer Counter will be turned off The Timer Counter Prescaler Prescaler will be cleared Input/Output Ports I/O ports will be setup as inputs Stack Pointer will point to the Stack Pointer top of the stack 63 HT45R37V October 20, 2009 ...
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... HT45R37V WDT Time-out (HALT ...
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... HT45R37V WDT Time-out (HALT ...
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... OSC1 and OSC2 pins are free for use as normal I/O pins. Refer to the Appendix section for more information on the actual internal oscil- lator frequency vs. Temperature and VDD characteris- tics graphics. 66 HT45R37V and 1. con- refer OSC October 20, 2009 ...
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... SLOW An additional sub internal clock, with the internal name 32kHz clock source which can be sourced from SUB either the internal 32K_INT oscillator or an external 32768Hz crystal, selected by configuration option. To- 67 HT45R37V whose source October 20, 2009 ...
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... IDLEN bit in the CLKMOD register. Switching to one of the lower power modes enables the normal operating current to be reduced to a lower operating level very low standby current level, a feature which is very important in low power battery applications. 68 HT45R37V /64 CPU on, f on, f SYS ...
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... Rev. 1.00 Dual Clock Mode Operation Dual Clock Mode Structure 69 HT45R37V October 20, 2009 ...
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... If the wake-up results in the execution of the next instruction following the HALT instruction, this will be executed immediately after the t period delay has ended. 70 HT45R37V SST system clock SST October 20, 2009 ...
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... Whether the Watchdog Timer clock source is its own in- ternal 32K_INT, the 32768Hz oscillator vided using configuration option to obtain the required Watchdog Timer time-out period. The max time out period is when the 2 71 HT45R37V or f /4. SUB SYS , which SUB /4 clock. SYS / di- ...
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... CLR WDT2 instruction will clear the Watchdog Timer. Similarly after the CLR WDT2 instruction has been executed, only a successive CLR WDT1 instruction can clear the Watchdog Timer. ¸ Watchdog Timer 72 HT45R37V October 20, 2009 ...
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... C debounce Time: no debounce, 1 system clock debounce, 2 system clock debounce Rev. 1.00 Options / HT45R37V October 20, 2009 ...
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... Timer/Event Counter and External Interrupt Pins Filter Option 23 Interrupt and Timer/Event Counter input pins internal filter On/Off control C Converter Option 24 I/O pins or C converter inputs Application Circuits C Application Circuit C Application Circuit Rev. 1.00 Options HT45R37V applies to all pins October 20, 2009 ...
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... C Application Circuit Note: 1. The *R resistance and *C capacitance should be consideration for the frequency of RC OSC are the resistance sensors. sensor sensor are the capacitance sensors. sensor sensor Rev. 1. HT45R37V October 20, 2009 ...
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... These instructions are the key to decision making and branching within the pro- gram perhaps determined by the condition of certain in- put switches or by the condition of internal data bits. 76 HT45R37V October 20, 2009 ...
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... Table conventions: x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Description 77 HT45R37V Cycles Flag Affected AC, OV Note AC AC ...
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... For the CLR WDT1 and CLR WDT2 instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both CLR WDT1 and CLR WDT2 instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged. Rev. 1.00 Description 78 HT45R37V Cycles Flag Affected 1 None Note 1 ...
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... Operation ACC ACC AND x Affected flag(s) Z ANDM A,[m] Logical AND ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical AND op- eration. The result is stored in the Data Memory. Operation [m] ACC AND [m] Affected flag(s) Z Rev. 1.00 79 HT45R37V October 20, 2009 ...
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... The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc- tion with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Re- petitively executing this instruction without alternately executing CLR WDT1 will have no effect. Operation WDT cleared TO 0 PDF 0 Affected flag(s) TO, PDF Rev. 1.00 addr 80 HT45R37V October 20, 2009 ...
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... This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. Operation TO 0 PDF 1 Affected flag(s) TO, PDF Rev. 1. HT45R37V October 20, 2009 ...
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... No operation is performed. Execution continues with the next instruction. Operation No operation Affected flag(s) None OR A,[m] Logical OR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical OR oper- ation. The result is stored in the Accumulator. Operation ACC ACC OR [m] Affected flag(s) Z Rev. 1.00 addr 82 HT45R37V October 20, 2009 ...
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... The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory re- main unchanged. Operation ACC.(i+1) ACC.0 [m].7 Affected flag(s) None Rev. 1.00 Stack Stack Stack [m]. 0~6) 83 HT45R37V October 20, 2009 ...
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... Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 re- places the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i [m].(i+1 0~6) ACC [m].0 Affected flag(s) C Rev. 1.00 [m]. 0~6) 84 HT45R37V October 20, 2009 ...
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... Set Data Memory Description Each bit of the specified Data Memory is set to 1. Operation [m] FFH Affected flag(s) None SET [m].i Set bit of Data Memory Description Bit i of the specified Data Memory is set to 1. Operation [m].i 1 Affected flag(s) None Rev. 1.00 [ HT45R37V October 20, 2009 ...
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... The result is stored in the Accumulator. Note that if the result of subtraction is nega- tive, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ACC Affected flag(s) OV, Z, AC, C Rev. 1.00 0 [m] [ HT45R37V October 20, 2009 ...
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... The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] program code (low byte) TBLH program code (high byte) Affected flag(s) None Rev. 1.00 [m].7 ~ [m].4 [m].7 ~ [m].4 [m].3 ~ [m].0 87 HT45R37V October 20, 2009 ...
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... The result is stored in the Data Memory. Operation [m] ACC XOR [m] Affected flag(s) Z XOR A,x Logical XOR immediate data to ACC Description Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. Operation ACC ACC XOR x Affected flag(s) Z Rev. 1.00 88 HT45R37V October 20, 2009 ...
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... Package Information 52-pin QFP (14mm´14mm) Outline Dimensions Symbol Rev. 1.00 Dimensions in mm Min. Nom. 17.3 13.9 17.3 13.9 1 0.4 2.5 0.1 0.73 0 HT45R37V Max. 17.5 14.1 17.5 14.1 3.1 3.4 1.03 0.2 7 October 20, 2009 ...
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... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.00 90 HT45R37V October 20, 2009 ...