HT36A1 Holtek Semiconductor Inc., HT36A1 Datasheet - Page 12

• Manufacturer Part Number: HT36A1
• Description: Ht36a1 -- Music Synthesizer 8-bit Mcu
• Manufacturer: Holtek Semiconductor Inc.

The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge sig-
nal on port A or a WDT overflow. An external reset
causes a device initialization and the WDT overflow per-
forms a warm reset . By examining the TO and PDF
flags, the cause for a chip reset can be determined. The
PDF flag is cleared when there is a system power-up or by
executing the CLR WDT instruction and it is set when a
HALT instruction is executed. The TO flag is set if the WDT
time-out occurs, and causes a wake-up that only resets
the program counter and stack pointer, the others remain
in their original status.
The port A wake-up and interrupt methods can be con-
sidered as a continuation of normal execution. Each bit
in port A can be independently selected to wake-up the
device by mask option. Awakening from an I/O port stim-
ulus, the program will resume execution of the next in-
struction. If awakening from an interrupt, two sequences
may occur. If the related interrupts is disabled or the in-
terrupts is enabled but the stack is full, the program will
resume execution at the next instruction. If the interrupt
is enabled and the stack is not full, a regular interrupt re-
sponse takes place.
Once a wake-up event occurs, it takes 1024 t
tem clock period) to resume to normal operation. In
other words, a dummy cycle period will be inserted after
the wake-up. If the wake-up results from an interrupt ac-
knowledge, the actual interrupt subroutine will be de-
layed by one more cycle. If the wake-up results in next
instruction execution, this will execute immediately after
a dummy period has finished. If an interrupt request flag
is set to 1 before entering the HALT mode, the
wake-up function of the related interrupt will be disabled.
To minimize power consumption, all I/O pins should be
carefully managed before entering the HALT status.
Reset
There are 3 ways in which a reset can occur:
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a warm re -
set that just resets the program counter and stack
pointer, leaving the other circuits to maintain their state.
Some registers remain unchanged during any other re-
Rev. 1.10
The WDT and WDT prescaler will be cleared and
starts to count again (if the clock comes from the WDT
oscillator).
All I/O ports maintain their original status.
The PDF flag is set and the TO flag is cleared.
The HALT pin will output a high level signal to disable
the external ROM.
RES reset during normal operation
RES reset during HALT
WDT time-out reset during normal operation
SYS
(sys-
12
set conditions. Most registers are reset to the initial
condition when the reset conditions are met. By exam-
ining the PDF and TO flags, the program can distinguish
between different chip resets .
Note: u stands for unchanged
To guarantee that the system oscillator has started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses during system
power up or when the system awakes from a HALT
state.
When a system power-up occurs, the SST delay is
added during the reset period. But when the reset co-
mes from the RES pin, the SST delay is disabled. Any
wake-up from HALT will enable the SST delay.
The functional units chip reset status are shown below.
Program Counter
Interrupt
Prescaler
WDT
Timer Counter (0/1)
Input/output ports
Stack Pointer
TO
0
u
0
1
1
PDF
0
u
1
u
1
RES reset during power-up
RES reset during normal operation
RES wake-up HALT
WDT time-out during normal operation
WDT wake-up HALT
Reset Timing Chart
Reset Circuit
RESET Conditions
000H
Disable
Clear
Clear. After master reset,
WDT begins counting
Off
Input mode
Points to the top of stack
March 12, 2007
HT36A1