HT36M4 Holtek Semiconductor Inc., HT36M4 Datasheet - Page 11

• Manufacturer Part Number: HT36M4
• Description: Ht36m4 -- Music Synthesizer 8-bit Mcu
• Manufacturer: Holtek Semiconductor Inc.

instruction. The software instructions include CLR
WDT and the other set
WDT2 . Of these two types of instructions, only one can
be active depending on the mask option
times selection option . If the CLR WDT is selected
(i.e. CLRWDT times equal one), any execution of the
WDT1 and CLR WDT2 are chosen (i.e. CLRWDT
times equal two), these two instructions must be exe-
cuted to clear the WDT; otherwise, the WDT may reset
the chip due to time-out.
Power Down Operation - HALT
The HALT mode is initialized by a HALT instruction and
results in the following:
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge sig-
nal on port A or a WDT overflow. An external reset
causes a device initialization and the WDT overflow per-
forms a warm reset . By examining the TO and PDF
flags, the cause for a chip reset can be determined. The
PDF flag is cleared when there is a system power-up or by
executing the CLR WDT instruction and it is set when a
HALT instruction is executed. The TO flag is set if a WDT
time-out occurs, and causes a wake-up that only resets
the Program Counter and Stack Pointer, the others remain
in their original status.
The port A wake-up and interrupt methods can be con-
sidered as a continuation of normal execution. Each bit
in port A can be independently selected to wake-up the
device by mask option. Awakening from an I/O port stim-
ulus, the program will resume execution of the next in-
struction. If awakening from an interrupt, two sequences
may occur. If the related interrupts is disabled or the in-
terrupts is enabled but the stack is full, the program will
resume execution at the next instruction. If the interrupt
is enabled and the stack is not full, a regular interrupt re-
sponse takes place.
Once a wake-up event occurs, it takes 1024 t
clock period) to resume to normal operation. In other
words, a dummy cycle period will be inserted after a
wake-up. If the wake-up results from an interrupt ac-
knowledge, the actual interrupt subroutine will be de-
Rev. 1.10
CLR WDT instruction will clear the WDT. In case CLR
The system oscillator will turn off but the WDT oscilla-
tor keeps running (if the WDT oscillator is selected).
Watchdog Timer
The contents of the on-chip RAM and registers remain
unchanged.
The WDT and WDT prescaler will be cleared and
starts to count again (if the clock comes from the WDT
oscillator).
All I/O ports maintain their original status.
The PDF flag is set and the TO flag is cleared.
The HALT pin will output a high level signal to disable
the external ROM.
WDT
CLR WDT1 and CLR
SYS
CLR WDT
(system
11
layed by one more cycle. If the wake-up results in next
instruction execution, this will be executed immediately
after a dummy period has finished. If an interrupt request
flag is set to 1 before entering the HALT mode, the
wake-up function of the related interrupt will be disabled.
To minimize power consumption, all I/O pins should be
carefully managed before entering the HALT status.
Reset
There are three ways in which a reset can occur:
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a warm re -
set that resets the Program Counter and Stack Pointer,
leaving the other circuits in their original state. Some
registers remain unchanged during other reset condi-
tions. Most registers are reset to the initial condition
when the reset conditions are met. By examining the
PDF and TO flags, the program can distinguish between
different chip resets .
RES reset during normal operation
RES reset during HALT
WDT time-out reset during normal operation
Reset Configuration
Reset Timing Chart
Reset Circuit
March 14, 2007
HT36M4