DSPIC30F3011 Microchip Technology Inc., DSPIC30F3011 Datasheet
DSPIC30F3011
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DSPIC30F3011 Summary of contents
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... Microchip Technology Inc. dsPIC30F3010/3011 Data Sheet High-Performance, 16-Bit Digital Signal Controllers DS70141D ...
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... Company’s quality system processes and procedures are for its PIC MCUs and dsPIC DSCs, K EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. ® L ® code hopping devices, Serial EE OQ © 2007 Microchip Technology Inc. ...
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... All DSP instructions single cycle • ± 16-bit single-cycle shift © 2007 Microchip Technology Inc. dsPIC30F3010/3011 Peripheral Features: • High-current sink/source I/O pins: 25 mA/25 mA • Timer module with programmable prescaler: - Five 16-bit timers/counters; optionally pair 16-bit timers into 32-bit timer modules • ...
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... Pins Mem. Bytes/ Bytes Instructions dsPIC30F2010 28 12K/4K 512 dsPIC30F3010 28 24K/8K 1024 dsPIC30F4012 28 48K/16K 2048 dsPIC30F3011 40/44 24K/8K 1024 dsPIC30F4011 40/44 48K/16K 2048 dsPIC30F5015 64 66K/22K 2048 dsPIC30F6010 80 144K/48K 8192 Note 1: This table provides a summary of the dsPIC30F3010/3011 peripheral features. Other available devices in the dsPIC30F Motor Control and Power Conversion Family are shown for feature comparison. ...
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... U2RX/CN17/RF4 13 U2TX/CN18/RF5 14 27 PGC/EMUC/U1RX/SDI1/SDA/RF2 15 26 PGD/EMUD/U1TX/SDO1/SCL/RF3 16 25 FLTA/INT0/RE8 17 24 SCK1/RF6 18 23 EMUC2/OC1/IC1/INT1/RD0 OC4/RD3 19 22 OC3/RD2 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 32 2 OSC2/CLKO/RC15 31 3 OSC1/CLKI dsPIC30F3011 AN8/RB8 AN7/RB7 26 8 AN6/OCFA/RB6 9 25 AN5/QEB/IC8/CN7/RB5 AN4/QEA/IC7/CN6/RB4 11 Confidential SS DD DS70141D-page 3 ...
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... Pin Diagrams (Continued) 44-Pin QFN PGC/EMUC/U1RX/SDI1/SDA/RF2 U2TX/CN18/RF5 U2RX/CN17/RF4 PWM3H/RE5 PWM3L/RE4 PWM2H/RE3 DS70141D-page RF1 5 29 RF0 6 dsPIC30F3011 Confidential OSC2/CLKO/RC15 OSC1/CLKI AN8/RB8 AN7/RB7 AN6/OCFA/RB6 AN5/QEB/IC8/CN7/RB5 AN4/QEA/IC7/CN6/RB4 ...
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... Pin Diagrams (Continued) 28-Pin SPDIP 28-Pin SOIC EMUD3/AN0/V REF EMUC3/AN1/V REF AN2/SS1/CN4/RB2 AN3/INDX/CN5/RB3 AN4/QEA/IC7/CN6/RB4 AN5/QEB/IC8/CN7/RB5 OSC2/CLKO/RC15 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 EMUD2/OC2/IC2/INT2/RD1 44-Pin QFN PGC/EMUC/U1RX/SDI1/SDA/RF2 PWM3H/RE5 PWM3L/RE4 PWM2H/RE3 © 2007 Microchip Technology Inc. dsPIC30F3010/3011 MCLR +/CN2/RB0 -/CN3/RB1 3 26 PWM1L/RE0 PWM1H/RE1 ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS70141D-page 6 Confidential © 2007 Microchip Technology Inc. ...
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... This document contains device specific information for the dsPIC30F3010/3011 device. devices contain extensive Digital Signal Processor (DSP) functionality within a high-performance 16-bit microcontroller (MCU) architecture. Figure 1-1 and Figure 1-2 show device block diagrams for the dsPIC30F3011 and dsPIC30F3010 devices. Confidential The dsPIC30F DS70141D-page 7 ...
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... FIGURE 1-1: dsPIC30F3011 BLOCK DIAGRAM Y Data Bus Interrupt PSV & Table Controller Data Access 8 24 Control Block 24 24 PCU PCH PCL Program Counter Stack Loop Address Latch Control Control Logic Logic Program Memory (24 Kbytes) Data EEPROM (1 Kbyte) 16 Data Latch ROM Latch ...
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... POR/BOR Reset MCLR Watchdog Timer Input Capture 10-bit ADC Module SPI Timers QEI © 2007 Microchip Technology Inc. dsPIC30F3010/3011 X Data Bus Data Latch Data Latch Y Data X Data RAM RAM 16 (4 Kbytes) (4 Kbytes) Address Address Latch ...
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... Multiple functions may exist on one port pin. When multiplexing occurs, the peripheral module’s functional requirements may force an override of the data direction of the port pin. TABLE 1-1: dsPIC30F3011 I/O PIN DESCRIPTIONS Pin Buffer Pin Name Type Type ...
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... TABLE 1-1: dsPIC30F3011 I/O PIN DESCRIPTIONS (CONTINUED) Pin Buffer Pin Name Type Type OSC1 I ST/CMOS OSC2 I/O — PGD I/O ST PGC I ST RB0-RB8 I/O ST RC13-RC15 I/O ST RD0-RD3 I/O ST RE0-RE5, I/O ST RE8 RF0-RF6 I/O ST SCK1 I/O ST SDI1 I ST SDO1 O — SS1 I ST SCL I/O ST SDA I/O ST SOSCO O — SOSCI I ST/CMOS T1CK I ST T2CK I ST ...
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... PWM 3 High output. Master Clear (Reset) input or programming voltage input. This pin is an active low Reset to the device. Compare Fault A input (for Compare channels and 4). Compare outputs 1 and 2. Analog = Confidential Analog input Output Power © 2007 Microchip Technology Inc. ...
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... CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input © 2007 Microchip Technology Inc. dsPIC30F3010/3011 Description Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. ...
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... NOTES: DS70141D-page 14 Confidential © 2007 Microchip Technology Inc. ...
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... Moreover, only the lower 16 bits of each instruction word can be accessed using this method. © 2007 Microchip Technology Inc. dsPIC30F3010/3011 • Linear indirect access of 32K word pages within program space is also possible using any working register, via table read and write instructions ...
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... The upper byte of the SR register contains the DSP adder/subtracter status bits, the DO Loop Active bit (DA) and the Digit Carry (DC) status bit. 2.2.3 PROGRAM COUNTER The Program Counter is 23 bits wide. Bit 0 is always clear. Therefore, the PC can address instruction words. Confidential © 2007 Microchip Technology Inc. ...
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... TBLPAG Data Table Page Address PSVPAG OAB SAB DA SRH © 2007 Microchip Technology Inc. dsPIC30F3010/3011 D15 D0 W0/WREG W10 W11 W12/DSP Offset W13/DSP Write Back W14/Frame Pointer ...
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... A block diagram of the DSP engine is shown in Figure 2-2. TABLE 2-2: Instruction CLR ED EDAC MAC MOVSAC MPY MPY.N MSC selection Confidential DSP INSTRUCTION SUMMARY Algebraic Operation – – change – – © 2007 Microchip Technology Inc. ...
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... FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In © 2007 Microchip Technology Inc. dsPIC30F3010/3011 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-bit Multiplier/Scaler 16 16 To/From W Array Confidential Round u Logic Zero Backfill DS70141D-page 19 ...
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... The OA and OB bits can also optionally generate an arithmetic warning trap when set and the correspond- ing overflow trap flag enable bit (OVATE, OVBTE) in the INTCON1 register (refer to Section 5.0) is set. This allows the user to take immediate action, for example, to correct system gain. Confidential © 2007 Microchip Technology Inc. ...
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... No saturation operation is performed and the accumulator is allowed to overflow (destroying its sign). If the COVTE bit in the INTCON1 register is set, a catastrophic overflow can initiate a trap exception. © 2007 Microchip Technology Inc. dsPIC30F3010/3011 2.4.2.2 Accumulator ‘Write Back’ The MAC class of instructions (with the exception of MPY, MPY ...
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... DSP shift operations and a 16-bit result for MCU shift operations. Data from the X bus is presented to the barrel shifter between bit positions for right shifts, and bit positions for left shifts. Confidential © 2007 Microchip Technology Inc. ...
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... TBLPAG<7> to determine user or configura- tion space access. In Table 3-1, Read/Write instruc- tions, bit 23 allows access to the Device ID, the User ID and the configuration bits. Otherwise, bit 23 is always clear. © 2007 Microchip Technology Inc. dsPIC30F3010/3011 FIGURE 3-1: PROGRAM SPACE MEMORY MAP FOR ...
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... Note: Program Space Visibility cannot be used to access bits <23:16> word in program memory. DS70141D-page 24 Program Space Address <23> <22:16> 0 TBLPAG<7:0> TBLPAG<7:0> 0 PSVPAG<7:0> 23 bits Program Counter Select bits 15 bits EA 8 bits 16 bits 24-bit EA Confidential <15> <14:1> <0> PC<22:1> 0 Data EA <15:0> Data EA <15:0> Data EA <14:0> 0 Byte Select © 2007 Microchip Technology Inc. ...
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... Program Memory ‘Phantom’ Byte (Read as ‘0’). © 2007 Microchip Technology Inc. dsPIC30F3010/3011 A set of Table Instructions are provided to move byte or word-sized data to and from program space. 1. TBLRDL: Table Read Low Word: Read the lsw of the program address ...
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... Execution prior to exiting the loop due to an interrupt - Execution upon re-entering the loop after an interrupt is serviced • Any other iteration of the REPEAT loop will allow the instruction, accessing data using PSV, to execute in a single cycle. Confidential 8 0 space addresses. The © 2007 Microchip Technology Inc. ...
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... The data space memory is split into two blocks, X and Y data space. A key element of this architecture is that Y space is a subset of X space, and is fully contained within X space. In order to provide an apparent linear addressing space, X and Y spaces have contiguous addresses. © 2007 Microchip Technology Inc. dsPIC30F3010/3011 Program Space 0x0000 (1) PSVPAG ...
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... Optionally Mapped into Program Memory 0xFFFF DS70141D-page 28 LSB 16 bits Address MSB LSB 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x09FE 0x0A00 Y Data RAM (Y) 0xBFE 0x0C00 0x8000 X Data Unimplemented (X) 0xFFFE Confidential 3072 bytes Near Data Space © 2007 Microchip Technology Inc. ...
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... DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS EXAMPLE SFR SPACE (Y SPACE) Non-MAC Class Ops (Read/Write) MAC Class Ops (Write) Indirect EA using any W © 2007 Microchip Technology Inc. dsPIC30F3010/3011 UNUSED Y SPACE UNUSED MAC Class Ops Read Only Indirect EA using W10, W11 Indirect EA using W8, W9 ...
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... FIGURE 3-8: MSB 15 0001 0x0000 0003 0x0000 0005 0x0000 Confidential ® DATA ALIGNMENT LSB Byte 1 Byte 0 0000 Byte 3 Byte 2 0002 Byte 5 Byte 4 0004 © 2007 Microchip Technology Inc. ...
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... Note push during exception processing will concatenate the SRL register to the MSB of the PC prior to the push. © 2007 Microchip Technology Inc. dsPIC30F3010/3011 There is a Stack Pointer Limit register (SPLIM) associ- ated with the Stack Pointer. SPLIM is uninitialized at Reset the case for the Stack Pointer, SPLIM<0> ...
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TABLE 3-3: CORE REGISTER MAP Address SFR Name Bit 15 Bit 14 Bit 13 Bit 12 (Home) W0 0000 W1 0002 W2 0004 W3 0006 W4 0008 W5 000A W6 000C W7 000E W8 0010 W9 0012 W10 0014 W11 ...
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TABLE 3-3: CORE REGISTER MAP (CONTINUED) Address SFR Name Bit 15 Bit 14 Bit 13 Bit 12 (Home) CORCON 0044 — — — US MODCON 0046 XMODEN YMODEN — XMODSRT 0048 XMODEND 004A YMODSRT 004C YMODEND 004E XBREV 0050 BREN ...
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... NOTES: DS70141D-page 34 Confidential © 2007 Microchip Technology Inc. ...
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... Register Indirect Register Indirect Post-modified Register Indirect Pre-modified Register Indirect with Register Offset The sum of Wn and Wb forms the EA. Register Indirect with Literal Offset © 2007 Microchip Technology Inc. dsPIC30F3010/3011 4.1.1 FILE REGISTER INSTRUCTIONS Most file register instructions use a 13-bit address field (f) to directly address data present in the first 8192 bytes of data memory (near data space) ...
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... The only exception to the usage restrictions is for buffers which have a power-of-2 length. As these buffers satisfy the start and end address criteria, they may operate in a Bidirectional mode, (i.e., address boundary checks will be performed on both the lower and upper address boundaries). Confidential © 2007 Microchip Technology Inc. ...
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... MODULO ADDRESSING OPERATION EXAMPLE Byte Address 0x1100 0x1163 Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words © 2007 Microchip Technology Inc. dsPIC30F3010/3011 4.2.2 W ADDRESS REGISTER SELECTION The Modulo and Bit-Reversed Addressing Control register MODCON<15:0> contains enable flags, as well register field to specify the W address registers ...
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... Sequential Address Bit Locations Swapped Left-to-Right Around Center of Binary Value Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-word Bit-Reversed Buffer Confidential N bytes, should not be enabled © 2007 Microchip Technology Inc. ...
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... TABLE 4-3: BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER Buffer Size (Words) 512 256 128 © 2007 Microchip Technology Inc. dsPIC30F3010/3011 Decimal ...
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... NOTES: DS70141D-page 40 Confidential © 2007 Microchip Technology Inc. ...
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... IPL bits. IPL<3> is present in the CORCON register, whereas IPL<2:0> are present in the STATUS Register (SR) in the processor core. © 2007 Microchip Technology Inc. dsPIC30F3010/3011 • INTCON1<15:0>, INTCON2<15:0> Global interrupt control functions are derived from these two registers. INTCON1 contains the control and status flags for the processor exceptions ...
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... PWM – PWM Period Match 40 48 QEI – QEI Interrupt 41 49 Reserved 42 50 Reserved 43 51 FLTA – PWM Fault Reserved 45-53 53-61 Reserved Lowest Natural Order Priority * Available on dsPIC30F3011 only Confidential © 2007 Microchip Technology Inc. Interrupt Source 2 C™ Slave Interrupt 2 C Master Interrupt ...
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... A momentary dip in the power supply to the device has been detected, which may result in malfunction. • Trap Lockout: Occurrence of multiple trap conditions simultaneously will cause a Reset. © 2007 Microchip Technology Inc. dsPIC30F3010/3011 5.3 Traps Traps can be considered as non-maskable interrupts indicating a software or hardware error, which adhere to a predefined priority as shown in Figure 5-1 ...
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... Stack Error Trap Vector Address Error Trap Vector Math Error Trap Vector Reserved Vector AIVT Reserved Vector Reserved Vector Interrupt 0 Vector Interrupt 1 Vector Interrupt 52 Vector Interrupt 53 Vector Confidential © 2007 Microchip Technology Inc. 0x000000 0x000002 0x000004 Reserved 0x000014 — — — 0x00007E 0x000080 Reserved ...
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... The RETFIE (Return from Interrupt) instruction will unstack the program counter and STATUS registers to return the processor to its state prior to the interrupt sequence. © 2007 Microchip Technology Inc. dsPIC30F3010/3011 5.5 Alternate Vector Table In Program Memory, the Interrupt Vector Table (IVT) is followed by the Alternate Interrupt Vector Table (AIVT), as shown in Figure 5-1 ...
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TABLE 5-2: INTERRUPT CONTROLLER REGISTER MAP SFR ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name INTCON1 0080 NSTDIS — — — — INTCON2 0082 ALTIVT DISI — — — IFS0 0084 CNIF MI2CIF SI2CIF NVMIF ADIF ...
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... Using NVMADR Addressing Using Table Instruction User/Configuration Space Select © 2007 Microchip Technology Inc. dsPIC30F3010/3011 6.2 Run-Time Self-Programming (RTSP) RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user may erase program memory, 32 instructions (96 bytes time and can write program memory data, 32 instructions (96 bytes time ...
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... NVMKEY register. Refer to Section 6.6 "Programming Operations" for further details. Note: The user can also directly write to the NVMADR and NVMADRU registers to specify a program memory address for erasing or programming. Confidential © 2007 Microchip Technology Inc. ...
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... MOV #0xAA,W1 MOV W1 NVMKEY , BSET NVMCON,#WR NOP NOP © 2007 Microchip Technology Inc. dsPIC30F3010/3011 4. Write 32 instruction words of data from data RAM “image” into the program Flash write latches. 5. Program 32 instruction words into program Flash. a) Setup NVMCON register for multi-word, program Flash, program and set WREN bit. ...
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... Write PM low word into program latch ; Write PM high byte into program latch ; Block all interrupts with priority <7 ; for next 5 instructions ; Write the 0x55 key ; ; Write the 0xAA key ; Start the erase sequence ; Insert two NOPs after the erase ; command is asserted Confidential © 2007 Microchip Technology Inc. ...
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TABLE 6-1: NVM REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 NVMCON 0760 WR WREN WRERR NVMADR 0762 NVMADRU 0764 — — — NVMKEY 0766 — — — ...
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... NOTES: DS70141D-page 52 Confidential © 2007 Microchip Technology Inc. ...
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... EEPROM write/erase operation. Attempting to read the data EEPROM while a programming or erase operation is in progress results in unspecified data. © 2007 Microchip Technology Inc. dsPIC30F3010/3011 Control bit WR initiates write operations, similar to pro- gram Flash writes. This bit cannot be cleared, only set, in software ...
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... Block all interrupts with priority <7 ; for next 5 instructions ; ; Write the 0x55 key ; ; Write the 0xAA key ; Initiate erase sequence ; Block all interrupts with priority <7 ; for next 5 instructions ; ; Write the 0x55 key ; ; Write the 0xAA key ; Initiate erase sequence Confidential © 2007 Microchip Technology Inc. ...
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... NOP ; Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle ; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete © 2007 Microchip Technology Inc. dsPIC30F3010/3011 The write will not initiate if the above sequence is not exactly followed (write 0x55 to NVMKEY, write 0xAA to NVMCON, then set WR bit) for each word ...
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... EEPROM writes, various mechanisms have been built-in. On power-up, the WREN bit is cleared; also, the Power-up Timer prevents EEPROM write. The write initiate sequence and the WREN bit together, help prevent an accidental write during brown-out, power glitch or software malfunction. Confidential © 2007 Microchip Technology Inc. ...
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... WR TRIS WR LAT + WR Port Read LAT Read Port © 2007 Microchip Technology Inc. dsPIC30F3010/3011 Any bit and its associated data and control registers that are not valid for a particular device will be disabled. That means the corresponding LATx and TRISx registers and the port pin will read as zeros. ...
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... Typically this instruction would be a NOP will be OL EXAMPLE 8-1: MOV 0xFF00, W0 MOV W0, TRISBB NOP btss PORTB, #13 Confidential I/O Cell I/O Pad Input Data PORT WRITE/READ EXAMPLE ; Configure PORTB<15:8> inputs ; and PORTB<7:0> as outputs ; Delay 1 cycle ; Next Instruction © 2007 Microchip Technology Inc. ...
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TABLE 8-1: dsPIC30F3010 PORT REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name TRISB 02C6 — — — — PORTB 02C8 — — — — LATB 02CA — — — — TRISC 02CC TRISC15 TRISC14 TRISC13 ...
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... TABLE 8-2: dsPIC30F3011 PORT REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name TRISB 02C6 — — — — PORTB 02C8 — — — — LATB 02CB — — — — TRISC 02CC TRISC15 TRISC14 TRISC13 — PORTC 02CE RC15 RC14 RC13 — ...
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... Legend uninitialized bit; — = unimplemented bit Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. Not all peripherals, and therefore their bit positions, are available on this device. © 2007 Microchip Technology Inc. dsPIC30F3010/3011 Bit 5 Bit 4 Bit 3 Bit 2 ...
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... NOTES: DS70141D-page 62 Confidential © 2007 Microchip Technology Inc. ...
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... Timer operation during CPU Idle and Sleep modes • Interrupt on 16-bit period register match or falling edge of external gate signal © 2007 Microchip Technology Inc. dsPIC30F3010/3011 These operating modes are determined by setting the appropriate bit(s) in the 16-bit SFR, T1CON. Figure 9-1 presents a block diagram of the 16-bit timer module. ...
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... Period register and be reset to 0x0000. When a match between the timer and the Period register occurs, an interrupt can be generated, if the respective Timer Interrupt Enable bit is asserted. Confidential TSYNC 1 Sync 0 TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 © 2007 Microchip Technology Inc. ...
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... XTAL SOSCO pF 100K © 2007 Microchip Technology Inc. dsPIC30F3010/3011 9.5.1 RTC OSCILLATOR OPERATION When the TON = 1, TCS = 1 and TGATE = 0, the timer increments on the rising edge of the 32 kHz LP oscilla- tor output signal the value specified in the Period register, and is then reset to ‘ ...
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TABLE 9-1: TIMER1 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — Legend uninitialized bit; — = unimplemented bit Note 1: Refer to ...
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... Interrupt on a 32-bit Period Register Match These operating modes are determined by setting the appropriate bit(s) in the 16-bit T2CON and T3CON SFRs. © 2007 Microchip Technology Inc. dsPIC30F3010/3011 For 32-bit timer/counter operation, Timer2 is the lsw and Timer3 is the msw of the 32-bit timer. ...
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... Timer Configuration bit T32, T2CON(<3>) must be set to 1 for a 32-bit timer/counter operation. All control bits are respective to the T2CON register. DS70141D-page 68 16 TMR2 Sync LSB PR2 Q D TGATE(T2CON<6> TON 1 X Gate 0 1 Sync Confidential TCKPS<1:0> 2 Prescaler 1, 8, 64, 256 © 2007 Microchip Technology Inc. ...
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... T3IF Event Flag 1 TGATE Note: The dsPIC30F3010/3011 devices do not have external pin inputs to TIMER3. In these devices the following modes should not be used: 1. TCS = 1 2. TCS = 0 and TGATE = 1 (Gated Time Accumulation) © 2007 Microchip Technology Inc. dsPIC30F3010/3011 PR2 TMR2 Q D TGATE Q CK ...
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... In this mode, the T3IF interrupt flag is used as the source of the interrupt. The T3IF bit must be cleared in software. Enabling an interrupt is accomplished via the respective Timer Interrupt Enable bit, T3IE (IEC0<7>). Confidential © 2007 Microchip Technology Inc. ...
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TABLE 10-1: TIMER2/3 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON — TSIDL — T3CON 0112 TON — TSIDL — Legend: u ...
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... NOTES: DS70141D-page 72 Confidential © 2007 Microchip Technology Inc. ...
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... The dsPIC30F3010/3011 devices do not have external pin inputs to TIMER4 or TIMER5. In these devices, the following modes should not be used: 1. TCS = 1 2. TCS = 0 and TGATE = 1 (Gated Time Accumulation) © 2007 Microchip Technology Inc. dsPIC30F3010/3011 The Timer4/5 module is similar in operation to the Timer 2/3 module. However, there are some differences, which are as follows: • ...
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... The dsPIC30F3010/3011 devices do not have external pin inputs to TIMER4 or TIMER5. In these devices, the following modes should not be used: 1. TCS = 1 2. TCS = 0 and TGATE = 1 (Gated Time Accumulation) DS70141D-page 74 PR4 TMR4 Q D TGATE Q CK TON 1 X Gate Sync Confidential Sync TCKPS<1:0> 2 Prescaler 1, 8, 64, 256 © 2007 Microchip Technology Inc. ...
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... Event Flag 1 TGATE Note: The dsPIC30F3010/3011 devices do not have external pin inputs to TIMER4 or TIMER5. In these devices, the following modes should not be used: 1. TCS = 1 2. TCS = 0 and TGATE = 1 (Gated Time Accumulation) © 2007 Microchip Technology Inc. dsPIC30F3010/3011 PR5 Comparator x 16 TMR5 Q D TGATE ...
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TABLE 11-1: TIMER4/5 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 TMR4 0114 TMR5HLD 0116 TMR5 0118 PR4 011A PR5 011C T4CON 011E TON — TSIDL — T5CON 0120 TON — TSIDL — Legend: u ...
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... ICxCON Data Bus Note: Where ‘x’ is shown, reference is made to the registers or bits associated to the respective input capture channels 1 through N. © 2007 Microchip Technology Inc. dsPIC30F3010/3011 The key operational features of the Input Capture module are: • Simple Capture Event mode • Timer2 and Timer3 mode selection • ...
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... The capture module must be configured for interrupt only on the rising edge (ICM<2:0> = 111) in order for the input capture module to be used while the device is in Sleep mode. The prescale settings of 4:1 or 16:1 are not applicable in this mode. Confidential © 2007 Microchip Technology Inc. ...
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... ICSIDL bit must be asserted to a logic ‘0’. If the input capture module is defined as ICM<2:0> = 111 in CPU Idle mode, the input capture pin will serve only as an external interrupt pin. © 2007 Microchip Technology Inc. dsPIC30F3010/3011 12.3 Input Capture Interrupts The input capture channels have the ability to generate an interrupt, based upon the selected number of capture events ...
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TABLE 12-1: INPUT CAPTURE REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 IC1BUF 0140 IC1CON 0142 — — ICSIDL — IC2BUF 0144 IC2CON 0146 — — ICSIDL — IC7BUF 0158 IC7CON 015A — — ICSIDL ...
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... TMR2<15:0 TMR3<15:0> Note: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels 1 through N. © 2007 Microchip Technology Inc. dsPIC30F3010/3011 The key operational features of the Output Compare module include: • Timer2 and Timer3 Selection mode • Simple Output Compare Match mode • ...
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... Fault condition has occurred. This state will be maintained until both of the following events have occurred: • The external Fault condition has been removed. • The PWM mode has been re-enabled by writing to the appropriate control bits. Confidential . © 2007 Microchip Technology Inc. ...
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... CPU Idle mode if the OCSIDL bit (OCxCON<13> logic 0 and the selected time base (Timer2 or Timer3) is enabled and the TSIDL bit of the selected timer is set to logic 0. © 2007 Microchip Technology Inc. dsPIC30F3010/3011 When the selected TMRx is equal to its respective period register, PRx, the following four events occur on the next increment cycle: • ...
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TABLE 13-1: OUTPUT COMPARE REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 OC1RS 0180 OC1R 0182 OC1CON 0184 — — OCSIDL — OC2RS 0186 OC2R 0188 OC2CON 018A — — OCSIDL — OC3RS* ...
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... INDX Digital Filter 3 Note 1: In dsPIC30F3010/3011, the UPDN pin is not available. Up/Down logic bit can still be polled by software. © 2007 Microchip Technology Inc. dsPIC30F3010/3011 The operational features of the QEI include: • Three input channels for two phase signals and index pulse • ...
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... UPDN signal is supplied to a SFR bit UPDN (QEICON<11> read- only bit. Note: QEI pins are multiplexed with analog inputs. User must insure that all QEI associated pins are set as digital inputs in the ADPCFG register. Confidential © 2007 Microchip Technology Inc. ...
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... CY To enable the filter output for channels QEA, QEB and INDX, the QEOUT bit must be ‘1’. The filter network for all channels is disabled on POR and BOR. © 2007 Microchip Technology Inc. dsPIC30F3010/3011 14.5 Alternate 16-bit Timer/Counter When the QEI module is not configured for the QEI mode QEIM< ...
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... The QEIIF bit must be cleared in software. QEIIF is located in the IFS2 status register. Enabling an interrupt is accomplished via the respec- tive Enable bit, QEIIE. The QEIIE bit is located in the IEC2 control register. QEISIDL bit Confidential © 2007 Microchip Technology Inc. ...
Page 91
TABLE 14-1: QEI REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name QEICON 0122 CNTERR — QEISIDL INDX UPDN DFLTCON 0124 — — — — POSCNT 0126 MAXCNT 0128 ADPCFG 02A8 — — ...
Page 92
... NOTES: DS70141D-page 90 Confidential © 2007 Microchip Technology Inc. ...
Page 93
... Uninterruptible Power Supply (UPS) The PWM module has the following features: • 6 PWM I/O pins with 3 duty cycle generators • 16-bit resolution © 2007 Microchip Technology Inc. dsPIC30F3010/3011 • ‘On-the-Fly’ PWM frequency changes • Edge and Center-Aligned Output modes • ...
Page 94
... Override Logic PWM Generator Channel 2 Dead-Time #2 Generator and Override Logic PWM Generator Channel 1 Dead-Time #1 Generator and Override Logic Special Event Postscaler PTDIR Confidential PWM3H PWM3L PWM2H Output PWM2L Driver Block PWM1H PWM1L FLTA Special Event Trigger © 2007 Microchip Technology Inc. ...
Page 95
... Electronically Commutative Motors (ECMs). The interrupt signals generated by the PWM time base depend on the mode selection bits (PTMOD<1:0>) and the postscaler bits (PTOPS<3:0>) in the PTCON SFR. © 2007 Microchip Technology Inc. dsPIC30F3010/3011 15.1.1 FREE-RUNNING MODE In the Free-Running mode, the PWM time base counts upwards until the value in the Time Base Period register (PTPER) is matched ...
Page 96
... PWM (PTMR Prescale Value) The maximum resolution (in bits) for a given device oscillator and PWM frequency can be determined using Equation 15-3: EQUATION 15-3: PWM RESOLUTION log (2 Resolution = Confidential © 2007 Microchip Technology Inc. be determined using • (PTPER + 1) • (PTPER + 0.75) • PWM CY log (2) ...
Page 97
... PWM period. In addition, the out- put on the PWM pin will be active for the entire PWM period if the value in the duty cycle register is equal to the value held in the PTPER register. © 2007 Microchip Technology Inc. dsPIC30F3010/3011 FIGURE 15-3: CENTER-ALIGNED PWM ...
Page 98
... On a write to the DTCON1 register. • On any device Reset. Note: The user should not modify the DTCON1 value while the PWM module is operating (PTEN = 1). Unexpected results may occur. Confidential © 2007 Microchip Technology Inc may ...
Page 99
... FIGURE 15-4: DEAD-TIME TIMING DIAGRAM Duty Cycle Generator PWMxH PWMxL Dead Time © 2007 Microchip Technology Inc. dsPIC30F3010/3011 Dead Time Confidential DS70141D-page 97 ...
Page 100
... PWM time base. Synchronous output overrides occur at the following times: • Edge-Aligned mode, when PTMR is zero. • Center-Aligned modes, when PTMR is zero and when the value of PTMR matches PTPER. Confidential © 2007 Microchip Technology Inc. contains six bits, ...
Page 101
... Fault pin could be used as a general purpose interrupt pin. The Fault pin has an interrupt vector, Interrupt Flag bit and Interrupt Priority bits associated with it. © 2007 Microchip Technology Inc. dsPIC30F3010/3011 15.12.2 Fault STATES The FLTACON special function register has 6 bits that determine the state of each PWM I/O pin when it is overridden by a Fault input ...
Page 102
... The PTCON SFR contains a PTSIDL control bit. This bit determines if the PWM module will continue to operate or stop when the device enters Idle mode. If PTSIDL = 0, the module will continue to operate. If PTSIDL = 1, the module will stop operation as long as the CPU remains in Idle mode. Confidential © 2007 Microchip Technology Inc. ...
Page 103
TABLE 15-1: PWM REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 PTCON 01C0 PTEN — PTSIDL — PTMR 01C2 PTDIR PTPER 01C4 — SEVTCMP 01C6 SEVTDIR PWMCON1 01C8 — — — — PWMCON2 01CA ...
Page 104
... NOTES: DS70141D-page 102 Confidential © 2007 Microchip Technology Inc. ...
Page 105
... Note: Both the transmit buffer (SPI1TXB) and the receive buffer (SPI1RXB) are mapped to the same register address, SPI1BUF. © 2007 Microchip Technology Inc. dsPIC30F3010/3011 In Master mode, the clock is generated by prescaling the system clock. Data is transmitted as soon as a value is written to SPI1BUF. The interrupt is generated at the middle of the transfer of the last bit ...
Page 106
... Clock Edge Control Select Enable Master Clock SDOx SDIy SDIx SDOy LSb Serial Clock SCKx SCKy Confidential Secondary Primary F Prescaler Prescaler CY 1:1 – 1 16, 64 SPI Slave Serial Input Buffer (SPIyBUF) Shift Register (SPIySR) MSb LSb PROCESSOR 2 © 2007 Microchip Technology Inc. ...
Page 107
... Therefore, when the SS1 pin is asserted low again, transmission/reception will begin at the MSb, even if SS1 has been de-asserted in the middle of a transmit/receive. © 2007 Microchip Technology Inc. dsPIC30F3010/3011 16.4 SPI Operation During CPU Sleep Mode During Sleep mode, the SPI module is shutdown ...
Page 108
TABLE 16-1: SPI1 REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name SPI1STAT 0220 SPIEN — SPISIDL — SPI1CON 0222 — FRMEN SPIFSD — DISSDO MODE16 SPI1BUF 0224 Legend uninitialized bit; ...
Page 109
... Thus, the I C module can operate either as a slave master bus. FIGURE 17-1: PROGRAMMER’S MODEL bit 15 bit 15 © 2007 Microchip Technology Inc. dsPIC30F3010/3011 17.1.1 VARIOUS I The following types • Slave operation with 7-bit address 2 • Slave operation with 10-bit address 2 • ...
Page 110
... Addr_Match I2CADD Start and Start, Restart, Collision Detect Acknowledge Generation Clock Stretching I2CTRN LSB Reload Control I2CBRG BRG Down Counter F CY Confidential Internal Data Bus Read Write Read Write Read Write Read Write Read Write Read © 2007 Microchip Technology Inc. ...
Page 111
... SDA is valid during SCL high (see timing diagram). The interrupt pulse is sent on the falling edge of the ninth clock pulse, regardless of the status of the ACK received from the master. © 2007 Microchip Technology Inc. dsPIC30F3010/3011 17.3.2 SLAVE RECEPTION If the R_W bit received is a ‘0’ during an address match, then Receive mode is initiated ...
Page 112
... This ensures that a write to the SCLREL bit will not violate the minimum high time requirement for SCL. If the STREN bit is ‘0’, a software write to the SCLREL bit will be disregarded and have no effect on the SCLREL bit. Confidential © 2007 Microchip Technology Inc. ...
Page 113
... When the interrupt is serviced, the source for the interrupt can be checked by reading the contents of the I2CRCV to determine if the address was device specific general call address. © 2007 Microchip Technology Inc. dsPIC30F3010/3011 2 17. Master Support As a Master device, six operations are supported: ...
Page 114
... Idle or continue on Idle. If I2CSIDL = 0, the module will continue operation on assertion of the Idle mode. If I2CSIDL = 1, the module will stop on Idle. Confidential 2 C master event Interrupt Service 2 C bus is free (i.e., the P bit is set) the 2 C bus © 2007 Microchip Technology Inc. ...
Page 115
TABLE 17-2: I C™ REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 — — — — I2CRCV 0200 — — — — I2CTRN 0202 — — — — I2CBRG 0204 — I2CCON 0206 ...
Page 116
... NOTES: DS70141D-page 114 Confidential © 2007 Microchip Technology Inc. ...
Page 117
... Data UxTX Parity Note dsPIC30F3010 only has UART1. © 2007 Microchip Technology Inc. dsPIC30F3010/3011 18.1 UART Module Overview The key features of the UART module are: • Full-duplex 9-bit data communication • Even, Odd or No Parity options (for 8-bit data) • ...
Page 118
... Receive Buffer Control – Generate Flags – Generate Interrupt – Shift Data Characters 8-9 Load RSR to Buffer Receive Shift Register (UxRSR) 16 Divider 16X Baud Clock from Baud Rate Generator Confidential Read Read Write UxMODE UxSTA Control Signals UxRXIF © 2007 Microchip Technology Inc. ...
Page 119
... The STSEL bit determines whether one or two Stop bits will be used during data transmission. The default (power-on) setting of the UART is 8 bits, no parity, 1 Stop bit (typically represented 1). © 2007 Microchip Technology Inc. dsPIC30F3010/3011 18.3 Transmitting Data 18.3.1 ...
Page 120
... UxRSR needs to transfer the character to the buffer. Once OERR is set, no further data is shifted in UxRSR (until the OERR bit is cleared in software or a Reset occurs). The data held in UxRSR and UxRXREG remains valid. Confidential © 2007 Microchip Technology Inc. RXB) X ...
Page 121
... FERR bit set. The break character is loaded into the buffer. No further reception can occur until a stop bit is received. Note that RIDLE goes high when the stop bit has not been received yet. © 2007 Microchip Technology Inc. dsPIC30F3010/3011 18.6 Address Detect Mode Setting the ADDEN bit (UxSTA< ...
Page 122
... For the UART, the USIDL bit selects if the module will stop operation when the device enters Idle mode, or whether the module will continue on Idle. If USIDL = 0, the module will continue operation during Idle mode. If USIDL = 1, the module will stop on Idle. Confidential © 2007 Microchip Technology Inc. ...
Page 123
TABLE 18-1: UART1 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 U1MODE 020C UARTEN — USIDL — U1STA 020E UTXISEL — — — UTXBRK UTXEN U1TXREG 0210 — — — — U1RXREG ...
Page 124
... NOTES: DS70141D-page 122 Confidential © 2007 Microchip Technology Inc. ...
Page 125
... SS REF ADC has a unique feature of being able to operate while the device is in Sleep mode. © 2007 Microchip Technology Inc. dsPIC30F3010/3011 The ADC module has six 16-bit registers: • A/D Control register 1 (ADCON1) • A/D Control register 2 (ADCON2) • A/D Control register 3 (ADCON3) • ...
Page 126
... AN8 *AN8 AN1 * = Not available on dsPIC30F3010. DS70141D-page 124 CH1 ADC S/H - 10-bit Result + CH2 S/H - 16-word, 10-bit + CH3 S/H CH1,CH2, - CH3,CH0 Sample/Sequence sample Input Switches + CH0 S/H - Confidential Conversion Logic Dual Port Buffer Control Input Mux Control © 2007 Microchip Technology Inc. ...
Page 127
... The channels are then converted sequentially. Obvi- ously, if there is only 1 channel selected, the SIMSAM bit is not applicable. © 2007 Microchip Technology Inc. dsPIC30F3010/3011 The CHPS bits selects how many channels are sam- pled. This can vary from channels. If CHPS selects 1 channel, the CH0 channel will be sampled at the sample clock and converted ...
Page 128
... – time AD = 5V). Refer to the Section 23.0 DD under AD A/D CONVERSION CLOCK CALCULATION T = 154 nsec nsec (30 MIPS – 154 nsec = 2 • – nsec = 8. (ADCS<5:0> nsec = ( 165 nsec © 2007 Microchip Technology Inc. ...
Page 129
... Up to 256. 300 ksps Note 1: External V - and V + pins must be used for correct operation. See Figure 19-2 for recommended REF REF circuit. © 2007 Microchip Technology Inc. dsPIC30F3010/3011 Table 19-1 R Max V Temperature S DD 500Ω 4.5V to 5.5V -40°C to +85°C 500Ω ...
Page 130
... DS70141D-page 128 The following figure depicts the recommended circuit for the conversion rates above 500 ksps dsPIC30F3011 ...
Page 131
... The A/D converts the value held on one S/H channel, while the second S/H channel acquires a new input sample. © 2007 Microchip Technology Inc. dsPIC30F3010/3011 19.7.3.2 Multiple Analog Input The A/D converter can also be used to sample multiple analog inputs using multiple sample and hold channels ...
Page 132
... Section 23.0 "Electrical Characteristics" for T sample time requirements ≤ 250Ω Sampling Switch leakage V = 0.6V T ± 500 nA negligible if Rs ≤ 5 kΩ. PIN Confidential period of sampling AD and AD ≤ 3 kΩ HOLD = DAC capacitance = 4 © 2007 Microchip Technology Inc. ...
Page 133
... Signed Integer d09 d09 d09 d09 d09 d09 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 Integer 0 © 2007 Microchip Technology Inc. dsPIC30F3010/3011 If the ADC interrupt is enabled, the device will wake-up from Sleep. If the ADC interrupt is not enabled, the ADC module will then be turned off, although the ADON bit will remain set ...
Page 134
... Any external components connected (via high impedance analog input pin (capacitor, zener diode, etc.) should have very little leakage current at the pin. Confidential and V as ESD the input voltage exceeds this SS © 2007 Microchip Technology Inc. ...
Page 135
TABLE 19-2: ADC REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 ADCBUF0 0280 — — — — ADCBUF1 0282 — — — — ADCBUF2 0284 — — — — ADCBUF3 0286 — — — ...
Page 136
... NOTES: DS70141D-page 134 Confidential © 2007 Microchip Technology Inc. ...
Page 137
... In the Idle mode, the clock sources are still active, but the CPU is shut-off. The RC oscillator option saves system cost, while the LP crystal option saves power. © 2007 Microchip Technology Inc. dsPIC30F3010/3011 20.1 Oscillator System Overview The dsPIC30F oscillator system has the following modules and features: • ...
Page 138
... MHz must be met oscillator can be conveniently shared as system clock, as well as real-time clock for Timer1. 3: Requires external R and C. Frequency operation MHz. DS70141D-page 136 Description (1) . (2) . (1) . (1) . (3) /4 output . OSC (3) . Confidential © 2007 Microchip Technology Inc. (1) . (1) . (1) . ...
Page 139
... FIGURE 20-1: OSCILLATOR SYSTEM BLOCK DIAGRAM OSC1 Primary Oscillator OSC2 TUN<3:0> 4 Internal Fast RC Oscillator (FRC) POR Done SOSCO 32 kHz LP Oscillator SOSCI © 2007 Microchip Technology Inc. dsPIC30F3010/3011 F PLL PLL x4, x8, x16 PLL Lock Primary Osc Primary Oscillator Stability Detector Oscillator Start-up Timer ...
Page 140
... OSC2 1 1 OSC2 0 1 OSC2 1 0 OSC2 1 1 OSC2 0 1 OSC2 1 0 OSC2 OSC2 0 0 OSC2 1 0 CLKO 1 1 CLKO OSC2 0 0 (Note (Note (Note © 2007 Microchip Technology Inc. ...
Page 141
... Table 20-4. If OSCCON<14:12> are set to ‘111’ and FPR<4:0> are set to ‘00101’, ‘00110’ or ‘00111’, then a PLL multi- plier (respectively) is applied © 2007 Microchip Technology Inc. dsPIC30F3010/3011 . Note: When a 16x PLL is used, the FRC fre- quency must not be tuned to a frequency greater than 7 ...
Page 142
... Byte Write “0x78” to OSCCON high Byte Write “0x9A” to OSCCON high Byte Write is allowed for one instruction cycle. Write the desired value or use bit manipulation instruction. Confidential © 2007 Microchip Technology Inc. ...
Page 143
... POR timer and place the device in the Reset state. The POR also selects the device clock source identified by the oscillator configuration fuses. © 2007 Microchip Technology Inc. dsPIC30F3010/3011 Different registers are affected in different ways by various Reset conditions. Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation ...
Page 144
... OST TIME-OUT PWRT TIME-OUT INTERNAL Reset FIGURE 20-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR OST TIME-OUT PWRT TIME-OUT INTERNAL Reset DS70141D-page 142 T OST T PWRT T OST T PWRT T OST T PWRT Confidential ) DD ): CASE CASE 2 DD © 2007 Microchip Technology Inc. ...
Page 145
... Note: The BOR voltage trip points indicated here are nominal values provided for design guidance only. © 2007 Microchip Technology Inc. dsPIC30F3010/3011 A BOR will generate a Reset pulse which will reset the device. The BOR will select the clock source, based on the device Configuration bit values (FOS<1:0> and FPR< ...
Page 146
... Microchip Technology Inc. ...
Page 147
... PWRSAV. These are: Sleep and Idle. The format of the PWRSAV instruction is as follows: PWRSAV <parameter>, where ‘parameter’ defines Idle or Sleep mode. © 2007 Microchip Technology Inc. dsPIC30F3010/3011 20.5.1 SLEEP MODE In Sleep mode, the clock to the CPU and peripherals is shut down ...
Page 148
... For additional information, please refer to the programming specifications of the device. Note: If the code protection configuration fuse bits (FGS<GCP> and FGS<GWRP>) have been programmed, an erase of the entire code-protected device is only possible at voltages V Confidential the Configuration bits is ≥ 4.5V. DD © 2007 Microchip Technology Inc. ...
Page 149
... MPLAB IDE. These pin pairs are named EMUD/EMUC, EMUD1/ EMUC1, EMUD2/EMUC2 and EMUD3/EMUC3. © 2007 Microchip Technology Inc. dsPIC30F3010/3011 In each case, the selected EMUD pin is the Emulation/ Debug Data line, and the EMUC pin is the Emulation/ Debug Clock line ...
Page 150
TABLE 20-7: SYSTEM INTEGRATION REGISTER MAP SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name . RCON 0740 TRAPR IOPUWR BGST — OSCCON 0742 TUN3 TUN2 COSC<1:0> TUN1 Legend uninitialized bit; — = unimplemented ...
Page 151
... The File register specified by the value ‘f’ • The destination, which could either be the File register ‘f’ or the W0 register, which is denoted as ‘WREG’ © 2007 Microchip Technology Inc. dsPIC30F3010/3011 Most bit oriented instructions (including simple rotate/ shift instructions) have two operands: • ...
Page 152
... Moreover, double-word moves require two cycles. The double-word instructions execute in two instruction cycles. Note: For more details on the instruction set, refer to the “dsPIC30F/33F Programmer’s Reference Manual” (DS70157). Description Confidential © 2007 Microchip Technology Inc. ...
Page 153
... Y data space Prefetch Address register for DSP instructions Wy ∈ {[W10]+=6, [W10]+=4, [W10]+=2, [W10], [W10]-=6, [W10]-=4, [W10]-=2, [W11]+=6, [W11]+=4, [W11]+=2, [W11], [W11]-=6, [W11]-=4, [W11]-=2, [W11+W12], none} Y data space Prefetch Destination register for DSP instructions ∈ {W4..W7} Wyd © 2007 Microchip Technology Inc. dsPIC30F3010/3011 Description Confidential DS70141D-page 151 ...
Page 154
... Branch if accumulator B overflow Branch if Overflow Branch if accumulator A saturated Branch if accumulator B saturated Branch Unconditionally Branch if Zero Computed Branch Bit Set f Bit Set Ws Write C bit to Ws<Wb> Write Z bit to Ws<Wb> Bit Toggle f Bit Toggle Ws Confidential © 2007 Microchip Technology Inc Status Flags cycle words Affected OA,OB,SA, C,DC,N,OV,Z ...
Page 155
... DEC2 DEC2 f DEC2 f,WREG DEC2 Ws,Wd 28 DISI DISI #lit14 © 2007 Microchip Technology Inc. dsPIC30F3010/3011 Description Bit Test f, Skip if Clear Bit Test Ws, Skip if Clear Bit Test f, Skip if Set Bit Test Ws, Skip if Set Bit Test f Bit Test Bit Test Bit Test Ws<Wb> Bit Test Ws< ...
Page 156
... Move WREG to f Move Double from W(ns):W( Move Double from Ws to W(nd ):W(nd) +1 Pre-fetch and store accumulator Multiply Accumulator Square Wm to Accumulator Multiply and Subtract from Accumulator Confidential © 2007 Microchip Technology Inc Status Flags cycle words Affected N,Z, ...
Page 157
... SETM WREG SETM Ws 70 SFTAC SFTAC Acc,Wn SFTAC Acc,#Slit6 © 2007 Microchip Technology Inc. dsPIC30F3010/3011 Description {Wnd+1, Wnd} = signed(Wb) * signed(Ws) {Wnd+1, Wnd} = signed(Wb) * unsigned(Ws) {Wnd+1, Wnd} = unsigned(Wb) * signed(Ws) {Wnd+1, Wnd} = unsigned(Wb) * unsigned(Ws) {Wnd+1, Wnd} = signed(Wb) * unsigned(lit5) {Wnd+1, Wnd} = unsigned(Wb) * unsigned(lit5) ...
Page 158
... Read Prog<23:16> to Wd<7:0> Read Prog<15:0> Write Ws<7:0> to Prog<23:16> Write Ws to Prog<15:0> Unlink frame pointer .XOR. WREG WREG = f .XOR. WREG Wd = lit10 .XOR .XOR .XOR. lit5 Wnd = Zero-Extend Ws Confidential © 2007 Microchip Technology Inc Status Flags cycle words Affected C,N,OV,Z 1 ...
Page 159
... PICSTART Plus Development Programmer - MPLAB PM3 Device Programmer - PICkit™ 2 Development Programmer • Low-Cost Demonstration and Development Boards and Evaluation Kits © 2007 Microchip Technology Inc. dsPIC30F3010/3011 22.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market ...
Page 160
... MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. ® DSCs on an instruction © 2007 Microchip Technology Inc. ...
Page 161
... The PC platform and Microsoft Windows 32-bit operating system were chosen to best make these features available in a simple, unified application. © 2007 Microchip Technology Inc. dsPIC30F3010/3011 22.9 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD ...
Page 162
... Check the Microchip web page (www.microchip.com) and the latest “Product Selector Guide” (DS00148) for the complete list of demonstration, development and evaluation kits. ® L security ICs, CAN ® battery management, SEEVAL © 2007 Microchip Technology Inc. ...
Page 163
... OPERATING MIPS VS. VOLTAGE V Range Temp Range DD 4.5-5.5V -40°C to 85°C 4.5-5.5V -40°C to 125°C 3.0-3.6V -40°C to 85°C 3.0-3.6V -40°C to 125°C 2.5-3.0V -40°C to 85°C © 2007 Microchip Technology Inc. dsPIC30F3010/3011 (except V and MCLR) (Note 1) ..................................... -0. ....................................................................................................... 0V to +13.25V ) .......................................................................................................... ± > ...................................................................................................± dsPIC30F301x-30I 30 — ...
Page 164
... Max Unit Notes 42 °C °C °C °C °C/W 1 -40°C ≤ T ≤ +85°C for Industrial A -40°C ≤ T ≤ +125°C for Extended A Units Conditions V Industrial temperature V Extended temperature V V V/ms 0-5V in 0.1 sec 0- © 2007 Microchip Technology Inc. ...
Page 165
... All I/O pins are configured as Inputs and pulled to V MCLR = V , WDT, FSCM, LVD and BOR are disabled. CPU, SRAM, Program Memory and Data DD Memory are operational. No peripheral modules are operating. © 2007 Microchip Technology Inc. dsPIC30F3010/3011 ) DD Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40° ...
Page 166
... Confidential 0.128 MIPS LPRC (512 kHz) (1.8 MIPS) FRC (7.37MHz) 4 MIPS 10 MIPS 20 MIPS 30 MIPS © 2007 Microchip Technology Inc. ...
Page 167
... These parameters are characterized but not tested in manufacturing. 3: These values represent the difference between the Base Power-Down Current and the Power-Down current with the specified peripheral enabled during Sleep. © 2007 Microchip Technology Inc. dsPIC30F3010/3011 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40° ...
Page 168
... SMbus disabled V SMbus enabled μ 5V PIN SS μA ≤ V ≤ PIN DD Pin at high-impedance μA ≤ V ≤ PIN DD Pin at high-impedance μA ≤ V ≤ PIN DD μA ≤ V ≤ XT PIN DD and LP Osc mode © 2007 Microchip Technology Inc. ...
Page 169
... These parameters are characterized but not tested in manufacturing. FIGURE 23-1: BROWN-OUT RESET CHARACTERISTICS V DD BO10 (Device in Brown-out Reset) Reset (due to BOR) © 2007 Microchip Technology Inc. dsPIC30F3010/3011 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T (1) Min Typ ...
Page 170
... Using EECON to read/write V = Minimum operating MIN voltage ms Year Provided no other specifications are violated mA Row Erase -40°C ≤ T ≤ +85°C E Minimum operating MIN voltage Year Provided no other specifications are violated ms mA Row Erase mA Bulk Erase © 2007 Microchip Technology Inc. ...
Page 171
... LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 - for all pins except OSC2 Pin FIGURE 23-3: EXTERNAL CLOCK TIMING Q4 OSC1 CLKO © 2007 Microchip Technology Inc. dsPIC30F3010/3011 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T Operating voltage V range as described in DC Spec Section 23.1 "DC DD Characteristics" ...
Page 172
... MHz XT MHz XT with 4x PLL MHz XT with 8x PLL MHz XT with 16x PLL MHz HS kHz LP MHz FRC internal kHz LPRC internal — See parameter OS10 for F value OSC ns See Table 23- See parameter D031 ns See parameter D032 ). CY © 2007 Microchip Technology Inc. ...
Page 173
... AC CHARACTERISTICS Operating temperature Param Characteristic No. OS61 x4 PLL x8 PLL x16 PLL Note 1: These parameters are characterized but not tested in manufacturing. © 2007 Microchip Technology Inc. dsPIC30F3010/3011 = 2 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature A -40°C ≤ (1) ...
Page 174
... Instruction Execution Frequency: MIPS = (F DS70141D-page 172 (3) (3) MIPS MIPS (2) (μsec) w/o PLL w PLL x4 20.0 0.05 — 1.0 1.0 4.0 0.4 2.5 10.0 0.16 6.25 — 1.0 1.0 4.0 0.4 2.5 10.0 = 1/MIPS PLLx)/4 since there are 4 Q clocks per instruction cycle. OSC Confidential (3) (3) MIPS MIPS w PLL x8 w PLL x16 — — 8.0 16.0 20.0 — — — 8.0 16.0 20.0 — © 2007 Microchip Technology Inc. ...
Page 175
... Overall FRC variation can be calculated by adding the absolute values of jitter, accuracy and drift percentages. TABLE 23-18: INTERNAL RC ACCURACY AC CHARACTERISTICS Param Characteristic No. (1) LPRC @ Freq. = 512 kHz OS65 Note 1: Change of LPRC frequency as V © 2007 Microchip Technology Inc. dsPIC30F3010/3011 -40°C ≤ -40°C ≤ Min Typ Max Units (1) -40°C ≤ T — ...
Page 176
... T ≤ +85°C for Industrial Operating temperature A -40°C ≤ T ≤ +125°C for Extended A (1)(2)(3) (4) Min Typ Max — — — — — — CY Confidential Units Conditions ns — ns — ns — ns — . OSC © 2007 Microchip Technology Inc. ...
Page 177
... These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. 3: Refer to Figure 23-1 and Table 23-10 for BOR. © 2007 Microchip Technology Inc. dsPIC30F3010/3011 SY10 SY13 Note: Refer to Figure 23-2 for load conditions. Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40° ...
Page 178
... Band Gap Stable ≤ +85°C for Industrial A ≤ +125°C for Extended A Conditions Defined as the time between the instant that the band gap is enabled and the moment that the band gap reference voltage is stable. RCON<13> Status bit © 2007 Microchip Technology Inc. ...
Page 179
... Ft1 SOSC1/T1CK oscillator input frequency range (oscillator enabled by setting bit TCS (T1CON, bit 1)) TA20 T Delay from External TxCK Clock CKEXTMRL Edge to Timer Increment © 2007 Microchip Technology Inc. dsPIC30F3010/3011 Tx11 Tx10 Tx15 OS60 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40° ...
Page 180
... T — CY ≤ +85°C for Industrial A ≤ +125°C for Extended A Max Units Conditions — ns Must also meet parameter TC15 — ns Must also meet parameter TC15 — prescale value (1, 8, 64, 256) 1.5 — © 2007 Microchip Technology Inc. ...
Page 181
... TQCP Input Period TQ20 T Delay from External TQCK Clock CKEXTMRL Edge to Timer Increment Note 1: These parameters are characterized but not tested in manufacturing. © 2007 Microchip Technology Inc. dsPIC30F3010/3011 TQ11 TQ10 TQ15 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40° ...
Page 182
... Industrial ≤ +125°C for Extended Max Units Conditions — ns — ns — ns — ns — prescale value (1, 4, 16) ≤ +85°C for Industrial A ≤ +125°C for Extended A Units Conditions ns See parameter D032 ns See parameter D031 © 2007 Microchip Technology Inc. ...
Page 183
... No. OC15 T Fault Input to PWM I/O FD Change OC20 T Fault Input Pulse Width FLT Note 1: These parameters are characterized but not tested in manufacturing. © 2007 Microchip Technology Inc. dsPIC30F3010/3011 OC20 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) Min Typ Max Units — — ...
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... T (1) Min Typ Max Units — — — ns — — — ns — — — — ns Confidential ≤ +85°C for Industrial A ≤ +125°C for Extended A Conditions See parameter D032 See parameter D031 — — © 2007 Microchip Technology Inc. ...
Page 185
... Note 1: These parameters are characterized but not tested in manufacturing Index Channel Digital Filter Clock Divide Select bits. Refer to Section 16. “Quadrature Encoder Interface (QEI)” in the “dsPIC30F Family Reference Manual” (DS70046). © 2007 Microchip Technology Inc. dsPIC30F3010/3011 TQ36 TQ30 TQ31 ...
Page 186
... Extended A (1) Min Max Units — — — CY Confidential Conditions 16, 32, 64, 128 and 256 (Note 16, 32, 64, 128 and 256 (Note 2) ns — © 2007 Microchip Technology Inc. ...
Page 187
... These parameters are characterized but not tested in manufacturing. 2: The minimum clock period for SCK is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. 3: Assumes 50 pF load on all SPI pins. © 2007 Microchip Technology Inc. dsPIC30F3010/3011 SP10 SP21 SP20 SP21 ...
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... Extended A Max Units Conditions — ns — — ns — — ns See parameter D032 — ns See parameter D031 — ns See parameter D032 — ns See parameter D031 30 ns — — ns — — ns — — ns — © 2007 Microchip Technology Inc. ...
Page 189
... These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: Assumes 50 pF load on all SPI pins. © 2007 Microchip Technology Inc. dsPIC30F3010/3011 SP70 SP73 SP72 MSb ...
Page 190
... SP50 SCK X (CKP = 0) SP71 SCK X (CKP = 1) MSb SDO X SP30,SP31 SDI SDI X MSb IN SP41 SP40 Note: Refer to Figure 23-2 for load conditions. DS70141D-page 188 SP70 SP72 SP73 SP35 SP73 SP72 SP52 BIT14 - - - - - -1 LSb BIT14 - - - -1 LSb IN Confidential SP52 SP51 © 2007 Microchip Technology Inc. ...
Page 191
... The minimum clock period for SCK is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPI pins. © 2007 Microchip Technology Inc. dsPIC30F3010/3011 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) ...
Page 192
... C™ BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 SCL IM11 IM10 SDA In IM40 SDA Out Note: Refer to Figure 23-2 for load conditions. DS70141D-page 190 IM11 IM10 IM26 IM25 IM40 Confidential IM34 IM33 Stop Condition IM21 IM33 IM45 © 2007 Microchip Technology Inc. ...
Page 193
... BRG is the value of the I C™ Baud Rate Generator. Refer to Section 21 “Inter-Integrated Circuit (I in the “dsPIC30F Family Reference Manual” (DS70046). 2: Maximum pin capacitance = 10 pF for all I © 2007 Microchip Technology Inc. dsPIC30F3010/3011 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature ...
Page 194
... MHz. μs — μs Device must operate at a minimum of 1.5 MHz μs Device must operate at a minimum of 10 MHz μs — specified to be from 400 specified to be from 400 © 2007 Microchip Technology Inc. ...
Page 195
... Bus Free Time BF SDA IS50 C Bus Capacitive B Loading Note 1: Maximum pin capacitance = 10 pF for all I © 2007 Microchip Technology Inc. dsPIC30F3010/3011 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T ≤ +85°C for Industrial Operating temperature A -40°C ≤ T ≤ +125°C for Extended ...
Page 196
... REFL REFH LSb 0V, INL SS REFL REFH LSb 0V, INL SS REFL REFH LSb 0V, INL SS REFL REFH LSb 0V, INL SS REFL REFH © 2007 Microchip Technology Inc. ...
Page 197
... These parameters are characterized but not tested in manufacturing. 2: Measurements taken with external V 3: The A/D conversion result never decreases with an increase in the input voltage, and has no missing codes. © 2007 Microchip Technology Inc. dsPIC30F3010/3011 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40° ...
Page 198
... Software clears ADCON. SAMP to start conversion. 4 — Sampling ends, conversion sequence starts. 5 — Convert bit 9. 6 — Convert bit 8. 8 — Convert bit 0. 9 — One T for end of conversion. AD DS70141D-page 196 AD55 Confidential AD55 © 2007 Microchip Technology Inc. ...
Page 199
... Software sets ADCON. ADON to start AD operation. 2 — Sampling starts after discharge period described in the “dsPIC30F SAMP Family Reference Manual”, (DS70046), Section 17, “10-bit A/D Converter”. 3 — Convert bit 9. 4 — Convert bit 8. © 2007 Microchip Technology Inc. dsPIC30F3010/3011 AD55 AD55 ...
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... — 0.5 T — AD — 20 — Confidential ≤ +85°C for Industrial A ≤ +125°C for Extended A Conditions (1) ns See Table 20-2 ns — — — (1) See Table 20-2 (1) — See Table 20-2 — — — — — — μs — © 2007 Microchip Technology Inc. ...