EM65571 ELAN Microelectronics Corp, EM65571 Datasheet - Page 55

• Manufacturer Part Number: EM65571
• Description: 130com / 128seg 65k Color Stn Lcd Driver
• Manufacturer: ELAN Microelectronics Corp

Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
7.16
7.17
7.18
7.19
The display timing circuit generates internal signals and timing pulses (internal LP, FLM, M)
by clock. It can select external input (CK) or internal oscillation.
Both the clock for the line counter and the clock to display the data latching circuit from the
display clock (internal LP) are generated. Synchronized with the display clock (internal LP),
the line addresses of the Display RAM are generated and 384-bit display data are latched
to display the data latching circuit and output to the LCD drive circuit (segment output).
Read-out of the display data to the LCD drive circuit is completely independent of the MPU.
The LCD alternated signal (internal M) and synchronous signal (internal FLM) are
generated by the display clock (internal LP). The FLM generates an alternated drive
waveform to the LCD drive circuit. Normally, the FLM generates alternated drive waveform
every frame (M-signal level is reversed every one frame). However, by setting up data
(n-1) in an n-line reverse register and n-line alternated control bit (NLIN) at “1”, an n-line
reverse waveform is generated.
The display data latching circuit temporally latches the display data that is output to the
LCD driver circuit from the display RAM, once every one common period. Normal
display/reverse display, display ON/OFF, and display all on functions are operated by
controlling the data in the display data latch, therefore, no data within the display RAM
changes.
Display Timing Circuit
Signal Generation to Display Line Counter and Display Data
Latching Circuit
Generation of the Alternated Signal (internal M) and the
Synchronous Signal (internal FLM)
Display Data Latching Circuit
FLM (internal)
LP (internal)
M (internal)
Symbol
LP or latched clock signal. At the rising edge, count the display line counter.
At the falling edge, output the LCD drive signal.
FLM or First Line Maker, signal for LCD display synchronous signals. When
FLM is set to “H”, the display start-line address is present.
Signal for LCD drive output alternated signals.
130COM/128SEG 65K Color STN LCD Driver
Description
EM65571
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