IR3081 International Rectifier Corp., IR3081 Datasheet - Page 11

• Manufacturer Part Number: IR3081
• Description: Xphasetm Vr 10 Control Ic
• Manufacturer: International Rectifier Corp.

IR3081 THEORY OF OPERATION
Block Diagram
The Block diagram of the IR3081 is shown in Figure 6, and specific features are discussed in the following sections.
VID Control
A 6-bit VID voltage compatible with VR 10, as shown in Table 1, is available at the VDAC pin. A detailed block
diagram of the VID control circuitry can be found in Figure 7. The VID pins require an external bias voltage and
should not be floated. The VID input comparators, with 0.6V reference, monitor the VID pins and control the 6 bit
Digital-to-Analog Converter (DAC) whose output is sent to the VDAC buffer amplifier. The output of the buffer
amplifier is the VDAC pin. The VDAC voltage is post-package trimmed to compensate for the input offsets of the
Error Amplifier to provide a 0.5% system set-point accuracy. The actual VDAC voltage does not determine the
system accuracy and has a wider tolerance.
ENABLE
VOSNS-
RMPOUT
SS/DEL
BBFB
VBIAS
ROSC
Page 11 of 39
VCC
VID5
VID0
VID1
VID2
VID3
VID4
9.1V
8.9V
+
-
50%
DUTY
CYCLE
IDISCHG
IROSC
IROSC
IROSC
IROSC
IROSC
IROSC
-
START
STOP
+
IROSC
VID
CONTROL
-
+
6uA
IROSC
IROSC
VCC
COMPARATOR
RAMP GENERATOR
ENABLE
COMPARATOR
+
-
UVLO
ICHG
70uA
VCHG
4V
ON
VID = 11111X
VID STEP-DOWN
VID DAC OUTPUT
SS/DEL
DISCHARGE
OFF
90mV
5.0V
1.0V
0.2V
Figure 6. IR3081 Block Diagram
DELAY
COMPARATOR
VBIAS
IROSC
-
+
+
-
DISCHARGE
COMPARATOR
0.6V
CURRENT
SOURCE
GENERATOR
1.3V
+
-
+
-
SOFTSTART
CLAMP
OVER
CURRENT
+
-
1.2V
ROSC
BUFFER
AMP
+
-
VBIAS
REGULATOR
IOCSET
+
-
COMPARATOR
OC
FAULT
LATCH
+
-
S
R
IROSC
+
-
6.8V
IROSC
DISABLE
+
+
-
IFB
-
+
10/01
ERROR
AMP
VDRP
AMP
IR3081
/04
PWRGD
VDRP
IIN
OCSET
EAOUT
FB
VDAC
LGND