MB15F02 Fujitsu Media Devices, MB15F02 Datasheet - Page 3

• Manufacturer Part Number: MB15F02
• Description: Dual Serial Input PLL Frequency Synthesizer
• Manufacturer: Fujitsu Media Devices

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SSOP
PIN DESCRIPTIONS
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
Pin No.
BCC
16
10
11
12
13
14
15
1
2
3
4
5
6
7
8
9
LD/fout
GND
OSCin
GND
name
Xfin
Vcc
Clock
Vcc
Do
PS
Data
PS
Do
fin
Pin
fin
LE
RF
IF
RF
RF
IF
IF
RF
RF
IF
RF
IF
I/O
O
O
O
–
–
–
–
I
I
I
I
I
I
I
I
I
Ground for RF–PLL section.
The programmable reference divider input. TCXO should be connected
with a coupling capacitor.
Ground for the IF-PLL section.
Prescaler input pin for the IF-PLL.
The connection with VCO should be AC coupling.
Power supply voltage input pin for the IF-PLL section.
Lock detect signal output (LD) / phase comparator monitoring output
(fout)
The output signal is selected by a LDS bit in a serial data.
LDS bit = ”H” ; outputs fout signal
LDS bit = ”L” ; outputs LD signal
Power saving mode control for the IF-PLL section. This pin must be set
at ”L” Power-ON. (Open is prohibited.)
PS
PS
Charge pump output for the IF-PLL section.
Phase characteristics of the phase detector can be reversed by FC-bit.
Charge pump output for the RF-PLL section.
Phase characteristics of the phase detector can be reversed by FC-bit.
Power saving mode control for the RF-PLL section. This pin must be set
at ”L” Power-ON. (Open is prohibited.)
PS
PS
Prescaler complimentary input for the RF-PLL section.
This pin should be grounded via a capacitor.
Power supply voltage input pin for the RF-PLL section, the shift register
and the oscillator input buffer.
Prescaler input pin for the RF-PLL.
The connection with VCO should be AC coupling.
Load enable signal input (with the schmitt trigger circuit.)
When LE is ”H”, data in the shift register is transferred to the
corresponding
Serial data input (with the schmitt trigger circuit.)
A data is transferred to the corresponding latch (IF-ref counter, IF-Prog.
counter, RF-ref. counter, RF-prog. counter) according to the control bit
in a serial data.
Clock input for the 23-bit shift register (with the schmitt trigger circuit.)
One bit data is shifted into the shift register on a riging edge of the
clock.
latch according to the control bit in a serial data.
IF
IF
RF
RF
= ”H” ; Normal mode
= ”L” ; Power saving mode
= ”H” ; Normal mode
= ”L” ; Power saving mode
Descriptions
MB15F02
3