MB15F02 Fujitsu Media Devices, MB15F02 Datasheet - Page 8

• Manufacturer Part Number: MB15F02
• Description: Dual Serial Input PLL Frequency Synthesizer
• Manufacturer: Fujitsu Media Devices

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8
MB15F02
Table2. Binary 14-bit Programmable Reference Counter Data Setting
Note:
Table.3 Test Purpose Bit Setting
LS
C
N
1
1
H
H
T
1
L
L
Divide
16383
ratio
Programmable Counter
(R)
Divide ratio less than 5 is prohibited.
C
N
2
5
6
2
CNT1, 2
N1 to N14
A1 to A7
SW
FC
LDS
NOTE: Start data input with MSB first.
L
D
S
3
W
S
4
H
H
T
2
L
L
14
R
0
0
1
C
5
F
: Control bit
: Divide ratio setting bits for the programmable counter (5 to 2,047)
: Divide ratio setting bits for the swallow counter (0 to 127)
: Divide ratio setting bit for the prescaler
: Phase control bit for the phase detector
: LD/fout signal select bit
(16/17 or 32/33 for the IF-PLL, 64/65 or 128/129 for the RF-PLL)
13
A
R
6
1
0
0
1
A
7
2
12
R
0
0
1
A
8
LD/fout pin state
3
Outputs fp
Outputs fr
Outputs fp
11
Outputs fr
R
0
0
1
A
9
4
Data
10
A
5
10
R
0
0
1
RF.
IF.
RF.
IF.
11
A
6
R
9
0
0
1
12
A
7
13
R
N
8
0
0
1
1
14
N
2
R
7
0
0
1
15
N
3
R
6
0
0
1
16
N
4
17
N
5
R
5
0
0
1
18
N
6
R
0
0
1
4
19
N
7
20
N
8
R
3
1
1
1
[Table. 1]
[Table. 4]
[Table. 5]
[Table. 6]
[Table. 7]
[Table. 8]
21
N
9
R
1
2
0
1
10
22 23
N
MS
11
N
R
1
1
0
1