STE2002_06 ST Microelectronics, Inc., STE2002_06 Datasheet
STE2002_06
Related parts for STE2002_06
STE2002_06 Summary of contents
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Features ■ 104 x 128 bits Display Data RAM ■ Programmable MUX rate ■ Programmable frame rate ■ X,Y Programmable carriage return ■ Dual partial display mode ■ Row by Row Scrolling ■ Automatic data RAM Blanking procedure ■ Selectable ...
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Contents Contents 1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STE2002 8 Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Pin description 1 Pin description Table 1. Pin description N° Pad Type 129-169 R0 to R80 O 282-322 ICON 323 C127 1-128 O V 236-255 GND SS V 188-199 Supply IC Positive Power Supply DD1 V 200-211 ...
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STE2002 Table 1. Pin description (continued) N° Pad Type R/W 219 I E 229 I PD/C 228 I SDIN 214 I SCLK 217 I SCE 216 I SD/C 215 I SOUT 213 O BSYFLG 212 O 170-179 T14 ...
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Pin description Figure 1. Chip mechanical drawing 6/61 MARK_1 COL 0 STE2002 VLCDOUT VLCDSENSE VLCDIN MARK_3 COL 63 (0,0) Y COL 64 X MARK_4 VDD2 VDD1 COL 127 MARK_2 STE2002 ROW 35 ROW 39. VLCDOUT VLCDSENSE VLCDIN OSCOUT TEST_14 TEST_13 ...
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STE2002 Figure 2. Improved ALTH & PLESKO driving method V LCD ROW LCD ROW ...
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Circuit description 2 Circuit description 2.1 Supplies voltages and grounds V is supply voltages to the internal voltage generator (see below). If the internal voltage DD2 generator is not used, this should be connected to V IC. V supply voltage ...
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STE2002 Figure 3. Bias level generator thus providing an 1/(n+4) ratio, with n calculated from: For and an 1/10 ratio is set. For and an 1/9 ratio is set. ...
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Circuit description 2.5 LCD voltage generation The LCD Voltage at reference temperature (To = 27°C) can be set using the VOP register content according to the following formula: V (T=To LCD LCD with the following values: Table 4. ...
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STE2002 2.6 Temperature coefficient As the viscosity, and therefore the contrast, of the LCD are subject to change with temperature, there's the need to vary the LCD Voltage with temperature. The STE2002 provides the possibility to change the VLCD in ...
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Display data RAM 3 Display data RAM The STE2002, provides an 104X128 bits Static RAM to store Display data. This is organized into 13 (Bank0 to Bank12) banks with 128 Bytes. One of these banks (128 bits wide) can be ...
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STE2002 When Y-Carriage>MUX lines, the icon row is moved in DDRAM to the first row of the Y- CARRIAGE Return BANK even always connected on the same output Driver. When MY=0, the icon Row is output on ...
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Display data RAM Figure 8. Automatic data RAM writing sequence with V=1 and Data RAM mirrored format (MX=1) Figure 9. Automatic data RAM writing sequence with X-Y carriage return (V=0; MX=0) Y CARR Figure 10. Automatic data RAM writing sequence ...
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STE2002 Figure 12. Automatic data RAM writing sequence with X-Y carriage return (V=1; MX=1) BANK 0 BANK 1 BANK 2 Y CARR BANK 11 BANK 12 Figure 13. Data RAM Byte organization with Figure 14. Data RAM ...
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Display data RAM Figure 16. Memory rows vs. row drivers mapping with MY=0, MUX 81, scroll pointer = +3, icon mode=1 ROW DRIVER ICON MODE ...
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STE2002 Figure 19. Memory rows vs. row drivers mapping with MUX65, Y-CARRIAGE>8, scroll pointer=0, icon mode=1 ROW DRIVER N. N. ICON Figure 20. Memory ...
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Display data RAM Figure 22. Memory rows vs. row drivers mapping with MY=1, MUX81, scroll offset = +3, icon mode =0 ROW DRIVER PHYSICAL MEMORY ROW ICON MODE=0 ROW ROW ROW ...
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STE2002 Figure 25. Row drivers vs. LCD panel interconnection in MUX65 mode Figure 26. Row drivers vs. LCD panel interconnection in MUX49 mode ICON 65x128 MUX 65 Mode COLUMN DRIVERS R40 R41 R42 R43 R44 R45 R46 R47 R48 R49 ...
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Display data RAM Figure 27. Row drivers vs. LCD panel interconnection in MUX33 mode 20/61 ICON 33x128 MUX 33Mode COLUMN DRIVERS R40 R41 R42 R43 R44 ROW DRIVERS R45 R46 R47 R48 R49 R50 R51 R52 R53 R54 R55 STE2002 ...
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STE2002 4 Instruction set Two different instructions formats are provided: - With D/C set to LOW commands are sent to the Control circuitry. - With D/C set to HIGH the Data RAM is addressed. Two different instruction set are embedded: ...
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Instruction set 4.3 Memory blanking procedure This instruction allows to fill the memory with "blank" patterns, in order to delete patterns randomly generated in memory when starting up the device. This instruction substitutes (128X13) single "write" instructions possible ...
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STE2002 Table 7. Scrolling function Mux rate Icon mode MUX 33 MUX 33 MUX 49 MUX 49 MUX 65 MUX 65 MUX 81 MUX 81 4.6 Dual partial display If the PE Bit is set to a logic one the ...
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Bus interfaces 5 Bus interfaces To provide the widest flexibility and ease of use the STE2002 features three different methods for interfacing the host Controller. To select the desired interface the SEL1 and SEL2 pads need to be connected to ...
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STE2002 By definition, a device that gives out a message is called "transmitter", the receiving device that gets the signals is called "receiver". The device that controls the message is called "master". The devices that are controlled by the master ...
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Bus interfaces 5.1.1 Communication protocol The STE2002 status read are allowed. Four are the device addresses available for the device. All have in common the first 5 bits (01111). The two least significant bit of the slave ...
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STE2002 Figure 30. Communication protocol WRITE MODE SLAVE ADDRESS READ MODE 5.2 Serial interface The STE2002 serial Interface is a bidirectional link ...
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Bus interfaces Figure 31. Serial bus protocol - one byte transmission SCE D/C SCLK SDIN Figure 32. Serial bus protocol - several byte transmission SCE D/C SCLK SDIN DB7 Figure 33. Serial bus protocol - several byte transmission SCE D/C ...
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STE2002 Figure 34. Reading sequence 5.3 Parallel interface The STE2002 parallel Interface is a bidirectional link between the display driver and the application supervisor. It consists of eleven lines: eight data lines (from DB7 to DB0) and three control lines. ...
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Bus interfaces Table 10. STE2001-like instruction set (continued) Instruction D/C R/W H=0 Memory Blank 0 0 Scroll Range LCD 0 0 Setting Display Control 0 0 Set CP Factor 0 0 Set RAM Set ...
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STE2002 Table 11. Extended instruction set Instruction B7 D/C R/W H independent instructions NOP Function Set Read Status Byte Write Data H=[0;0] RAM commands Memory ...
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Bus interfaces Table 11. Extended instruction set Instruction B7 D/C R/W H=[1; Partial mode H=[1; ...
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STE2002 Table 13. Page number H[1] H[ Table 14. Display mode Table 15. Frame rate control FR[1] FR[ ...
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Bus interfaces Table 18. Temperature coefficient Table 19. TC1 & TC0 temperature coefficients TC1 TC0 ...
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STE2002 O Table 21. Bias ratio BS2 BS1 BS0 Table 22. Y carriage return register Y-C[3] Y-C[2] Y-C[1] Y-C[ ...
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Bus interfaces Figure 35. Host processor interconnection with I2C interface Figure 36. Host processor interconnection with serial interface 36/61 SCL SDAIN µP SDAOUT STE2002 VSSAUX RES E PD R/W VSSAUX SCLK SCE ...
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STE2002 Figure 37. Host processor interconnection with parallel interface Figure 38. application schematic using an external lcd Voltage Generator Figure 39. Application schematic using the internal LCD voltage generator and two separate supplies SCL SDAIN SDAOUT STE2002 VSSAUX RES E ...
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Bus interfaces Figure 40. Application schematic using the internal LCD voltage generator and a single supply 38/61 I/O V VDD2 40 DD VDD1 100nF V VSS2 128 SS VSS1 1µF VLCDSENSE 41 VLCDOUT VLCDIN STE2002 81 x 128 DISPLAY ...
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STE2002 Figure 41. Power-up sequence VDD2 VDD1 RES SCE SCLK SDIN SD/C PD HOST DRIVER SCL SDAIN SOUT SDA OUT OSCIN (HOST) OSC OUT (DRIVER) BSY FLG vdd w(res) ...
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Bus interfaces Figure 42. Power-OFF sequence VDD2 VDD1 RES SCLK SDIN SD/C PD/C E SCE SCl SDAIN R HOST DRIVER SOUT SDA OUT OSCIN (HOST) OSC OUT (DRIVER) BSY FLG 40/61 T w(res) Hi-Z ...
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STE2002 Figure 43. Initialization with built-in booster Figure 44. Dual partial display enabling instruction flow SETUP NORMAL DISPLAY MODE CONFIGURATION SET Driver in Power Down(PD=1) SET Driver in Normal Display Mode (PE=0) SET PRS[1:0], Vop[6:0], BS[2:0], CP[2:0], FR[1:0], TC, M[1:0] ...
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Bus interfaces Figure 45. Dual partial display mode configuration or duty change Figure 46. Data RAM to display mapping DISPLAY DATA RAM 42/61 SETUP PARTIAL DISPLAY CONFIGURATION SET Driver in Power Down(PD=1) SET Driver in Partial Display Mode (PE=1) SET ...
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STE2002 Table 24. Pin configuration Test numbers TEST_1 TEST_2 TEST_3 TEST_4 TEST_5 TEST_6 TEST_7 TEST_8 TEST_9 TEST_10 TEST_11 TEST_12 TEST_13 TEST_14 Bus interfaces Pin configuration OPEN GND GND 43/61 ...
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Electrical characteristics 6 Electrical characteristics 6.1 Absolute maximum ratings Table 25. Absolute maximum ratings Symbol V Supply voltage range DD1 V Supply voltage range DD2 V LCD Supply Voltage Range LCD I Supply current SS V Input Voltage (all input ...
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STE2002 6.2 DC operation VDD1 = 1.7 to 3.6 V; VDD2 = 1.75 to 4.2V; Vss1,2 = 0V; VLCD = 4.5 to 14.5 V; Tamb = 25°C; unless otherwise specified. Table 26. Electrical characteristics DC operation Symbol Parameter Supply voltages ...
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Electrical characteristics Table 26. Electrical characteristics DC operation Symbol Parameter Logic inputs V Logic LOW voltage level IL V Logic HIGH voltage level IH I Input current in logic inputs/outputs V Logic LOW voltage level IL Logic HIGH Voltage V ...
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STE2002 6.3 AC operation VDD1 = 1.7 to 3.6V; VDD2 = 1.75 to 4.2V; Vss1,2 = 0V; VLCD = 4.5 to 14.5V; Tamb = 25°C; unless otherwise specified. Table 27. AC operation Symbol Parameter Figure 47 Internal oscillator ( ) ...
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Electrical characteristics Table 27. AC operation (continued) Symbol Parameter T Rise time of SDAH signal Cb=100pF rDA T Fall time of SDAH signal fDA T Rise time of SDAH signal Cb=400pF rDA T Fall time of SDAH signal fDA Set-up ...
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STE2002 Table 27. AC operation (continued) Symbol Parameter Figure 51 Serial interface ( ) T Clock Cycle SCLK CYC T SCLK pulse width HIGH PWH1 T SCLK Pulse width LOW PWL1 T SCE setup time S2 T SCE hold time ...
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Electrical characteristics Figure 47. RESET timing diagram 2 Figure 48. I C-bus timings 50/61 Tw(res) Tlogic(res) VDD2 VDD1 RES INPUTS I/O (HOST) I/O Hi-Z (DRIVER) INTERFACE Hi-Z OUTPUT OSCIN (HOST) OSC OUT (DRIVER) BSY FLG RESET TABLE LOADED Sr t ...
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STE2002 Figure 49. Parallel interface write timing Figure 50. Parallel interface read timing Figure 51. Serial interface timing 7 Pad coordinates See Table 28: Pad coordinates PD SU(A) W(en) h( SU(D) HO(D) DB0-DB7 R/W ...
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Pad coordinates Table 28. Pad coordinates Name Pad X (µ -3275 -3225 -3175 -3125 -3075 -3025 -2975 -2925 -2875 -2825.0 ...
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STE2002 Table 28. Pad coordinates (continued) Name Pad X (µm) C68 69 +325.0 C69 70 +375.0 C70 71 +425.0 C71 72 +475.0 C72 73 +525.0 C73 74 +575.0 C74 75 +625.0 C75 76 +675.0 C76 77 +725.0 C77 78 +775.0 ...
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Pad coordinates Table 28. Pad coordinates (continued) Name Pad X (µm) R50 139 +3571.5 R51 140 +3571.5 R52 141 +3571.5 R53 142 +3571.5 R54 143 +3571.5 R55 144 +3571.5 R56 145 +3571.5 R57 146 +3571.5 R58 147 +3571.5 R59 148 ...
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STE2002 Table 28. Pad coordinates (continued) Name Pad X (µm) VDD2_8 207 +1375.0 VDD2_9 208 +1325.0 VDD2_10 209 +1325.0 VDD2_11 210 +1275.0 VDD2_12 211 +1275.0 BUSY_FLAG 212 +1125.0 SDOUT 213 +975.0 SDIN 214 +925.0 SD/C 215 +875.0 SCE 216 +825.0 ...
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Pad coordinates Table 28. Pad coordinates (continued) Name Pad X (µm) VLCDOUT_3 275 -2675.0 VLCDOUT_4 276 -2675.0 VLCDOUT_5 277 -2725.0 VLCDOUT_6 278 -2725.0 VLCDOUT_7 279 -2775.0 VLCDOUT_8 280 -2775.0 VLCDOUT_9 281 -2825.0 VLCDOUT_10 282 -2825.0 R39 283 -3075.0 R38 284 ...
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STE2002 Table 29. Alignment marks coordinates X -3574.5 +3574.5 -2250 +1200 Figure 52. Alignment marks dimensions Y -949.5 -949.5 +949.5 +949.5 39 µm 94 µm Pad coordinates Marks mark1 mark2 mark3 mark4 57/61 ...
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Mechanical data 8 Mechanical data Table 30. Bumps Bumps on single row size Bumps on two rows size Pad size Pad pitch Spacing between bumps Table 31. Die mechanical dimensions Die size Wafers thickness Figure 53. Die orientation in tray ...
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STE2002 Figure 54. Tray information A A Mechanical data Array Size = 13 x5 (65) Units 59/61 ...
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Ordering information 9 Ordering information Table 32. Order codes Part numbers STE2002DIE1 STE2002DIE2 10 Revision history Table 33. Document revision history Date 15-Sep-2002 15-Sep- 2005 12-Dec-2006 60/61 Bumped wafers Bumped dice on waffle pack Revision 1 Initial release. Updated suppy ...
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STE2002 Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at ...