AD9381 Analog Devices, AD9381 Datasheet - Page 12

• Manufacturer Part Number: AD9381
• Description: HDMI Display Interface
• Manufacturer: Analog Devices

AD9381
AUDIO PLL SETUP
Data contained in the audio infoframes, among other registers,
define for the AD9381 HDMI receiver not only the type of
audio, but the sampling frequency (f
contains information about the N and CTS values used to
recreate the clock. With this information it is possible to
regenerate the audio sampling frequency. The audio clock is
regenerated by dividing the 20-bit CTS value into the TMDS
clock, then multiplying by the 20-bit N value. This yields a
multiple of the f
256 × f
Table 9. AD9398 Audio Register Settings
Register
0x01
0x02
0x03
0x34
0x58
128 ×
1
CLOCK
N AND CTS VALUES ARE TRANSMITTED USING THE
AUDIO CLOCK REGENERATION PACKET. VIDEO
CLOCK IS TRANSMITTED ON TMDS CLOCK CHANNEL.
VIDEO
N
f
S
s
. It is possible for this to be specified up to 1024 × f
REGISTER
DIVIDE
Bits
7:0
7:4
7:6
5:3
2
4
7
6:4
3
2:0
SOURCE DEVICE
BY
N
N
s
(sampling frequency) of either 128 × f
Figure 7. N and CTS for Audio Clock
Recommended
Setting
0x00
0x40
01
010
1
0
1
011
0
0**
COUNTER
CYCLE
TIME
CLOCK
TMDS
CTS
N
1
1
S
). The audio infoframe also
DIVIDE
CTS
BY
SINK DEVICE
Function
VCO Range
Charge Pump Current
PLL Enable
Audio Frequency Mode Override
PLL Enable
N/CTS Disable
MCLK Sampling Frequency
PLL Divisor (MSBs)
PLL Divisor (Lab’s)
MCLK PLL Divisor
MULTIPLY
BY
N
s
or
128 ×
s
.
Rev. 0 | Page 12 of 44
f
S
In order to provide the most flexibility in configuring the audio
sampling clock, an additional PLL is employed. The PLL
characteristics are determined by the loop filter design, the PLL
charge pump current, and the VCO range setting. The loop
filter design is shown in Figure 8.
To fully support all audio modes for all video resolutions up to
1080p, it is necessary to adjust certain audio-related registers
from their power-on default values. Table 9 describes these
registers and gives their recommended settings.
Comments
The analog video PLL is also used for the audio clock
circuit when in HDMI mode. This is done automatically.
In HDMI mode, this bit enables a lower frequency to be
used for audio MCLK generation.
Allows the chip to determine the low frequency mode
of the audio PLL.
This enables the analog PLL to be used for audio MCLK
generation.
When the analog PLL is enabled for MCLK generation,
another frequency divider is provided. These bits set
the divisor to 4.
The N and CTS values should always be enabled.
000 = 128 × f
001 = 256 × f
010 = 384 × f
011 = 512 × f
8nF
C
P
Figure 8. PLL Loop Filter Detail
S
S
S
S
FILT
1.5kΩ
R
Z
C
80nF
Z
PV
D