AD9381 Analog Devices, AD9381 Datasheet - Page 15

• Manufacturer Part Number: AD9381
• Description: HDMI Display Interface
• Manufacturer: Analog Devices

Hex
Address
0x25
0x26
0x27
Read/Write
or Read Only
Read/Write
Read/Write
Read/Write
Bits
[4]
[0]
[7:6]
[5:4]
[3:2]
[1]
[0]
[7]
[5]
[4]
[3]
[2:1]
[0]
[7]
[6]
[5]
[4]
[3]
******1*
****1***
*******0
Default Value
***1****
*******0
01******
**11****
****00**
*******0
0*******
**0*****
***0****
*****00*
1*******
*0******
**0*****
***0****
****0***
Register Name
Field Output Polarity
Output CLK Invert
Output CLK Select
Output Drive Strength
Output Mode
Primary Output Enable
Secondary Output
Enable
Output Three-State
SPDIF Three-State
I
Power-Down Pin Polarity
Power-Down Pin
Function
Power-Down
Auto Power-Down
Enable
HDCP A0
MCLK External Enable
BT656 EN
Force DE Generation
2
S Three-State
Rev. 0 | Page 15 of 44
Description
Output field polarity.
0 = active low out.
1 = active high out.
0 = don’t invert clock out.
1 = invert clock out.
Selects which clock to use on output pin. 1× CLK is
divided down from TMDS clock input when pixel
repetition is in use.
00 = ½× CLK.
01 = 1× CLK.
10 = 2× CLK.
11 = 90° phase 1× CLK.
Sets the drive strength of the outputs.
00 = lowest, 11 = highest.
Selects the data output mapping.
00 = 4:4:4 mode (normal).
01 = 4:2:2 + DDR 4:2:2 on blue.
10 = DDR 4:4:4 + DDR 4:2:2 on blue.
11 = 12-bit 4:2:2 (HDMI option only).
Enables primary output.
Enables secondary output (DDR 4:2:2 in Output
Mode 1 and Mode 2).
Three-state the outputs.
Three-state the S/PDIF output.
Three-state the I
Sets polarity of power-down pin.
0 = active low.
1 = active high.
Selects the function of the power-down pin.
00 = power-down.
01 = power-down and three-state SOG.
10 = three-state outputs only.
11 = three-state outputs and SOG.
0 = normal.
1 = power-down.
0 = disable auto low power state.
1 = enable auto low power state.
Sets the LSB of the address of the HDCP I
Set to 1 only for a second receiver in a dual-link
configuration.
0 = use internally generated MCLK.
1 = use external MCLK input.
If an external MCLK is used, it must be locked to the
video clock according to the CTS and N available in
the I2C. Any mismatch between the internal MCLK
and the input MCLK results in dropped or repeated
audio samples.
Enables EAV/SAV codes to be inserted into the
video output data.
Allows use of the internal DE generator in DVI
mode.
2
S output and the MCLK out.
AD9381
2
C.