CY3138R62 Cypress Semiconductor Corp., CY3138R62 Datasheet

CY3138R62

Manufacturer Part Number

CY3138R62

Description

Warp Enterprise Verilog PC

Manufacturer

Cypress Semiconductor Corp.

Datasheet

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Cypress Semiconductor Corporation

Document #: 38-03045 Rev. *A

Features

• Verilog (IEEE 1364) high-level language compilers with

• Several design entry methods support high-level and

• Language Assistant library of Verilog templates

• Flow Manager Interface to keep track of complex

• UltraGen™ Synthesis and Fitting Technology:

• Support for all Cypress Programmable Logic Devices

• VHDL or Verilog timing model output for use with

• Active-HDL™ Sim Release 4.1 timing simulation from

the following features:

low-level design descriptions:

projects

third-party simulators

Aldec

— Designs are portable across multiple devices

— Facilitates the use of industry-standard simulation

— Support for functions and libraries facilitating mod-

— Support for reduction and conditional operators,

— Graphical HDL Block Diagram editor with a library of

— Aldec Active-HDL™ FSM graphical Finite State

— Behavioral Verilog (IF...THEN...ELSE; CASE...)

— Boolean

— Structural Verilog

— Designs can include multiple entry methods (but

— Infers “modules” such as adders, comparators, etc.,

— User-selectable speed and/or area optimization on a

— Perfectly integrated synthesis and fitting

— Automatic selection of optimal flip-flop type

— Automatic pin assignment

— PSI™ (Programmable Serial Interface)

— Delta39K™ CPLDs

— Quantum38K™ CPLDs

— Ultra37000™ CPLDs

— F

— MAX340™ CPLDs

— Industry standard PLDs (16V8, 20V8, 22V10)

and/or EDA environments

and synthesis tools for board- and system-level de-

sign

ular design methodology

blocking and non-blocking procedural assignments,

while loops and integers

blocks and a text-to-block conversion utility from Al-

dec

Machine editor

only one HDL) in a single design.

from behavioral descriptions and replaces them with

circuits pre-optimized for the target device.

block-by-block basis

(D type/T type)

LASH

370i™ CPLDs

Warp Enterprise™ Verilog CPLD Software

•

3901 North First Street

Functional Description

Warp Enterprise™ is an integration of the Warp Enterprise

CPLD Development package with additional sophisticated

EDA software features from Aldec. In addition to accepting

IEEE 1364 Verilog text and graphical finite state machines for

design entry, Warp Enterprise Verilog provides a graphical

HDL block diagram editor with a library of graphical HDL

blocks pre-optimized for Cypress devices. Plus, it provides a

utility to convert HDL text into graphical HDL blocks. Warp

Enterprise synthesizes and optimizes the entered design, and

outputs a JEDEC or Intel hex file for the desired PLD or CPLD

(see Figure 1). For simulation, Warp Enterprise provides a tim-

ing simulator, a source-level behavioral simulator, as well as

VHDL and Verilog timing models for use with third party simu-

lators. Warp Enterprise also provides the designer with impor-

tant productivity tools such as a testbench generation wizard

and the Architecture Explorer graphical analysis tool.

Verilog Compiler

Verilog is a powerful, industry-standard language for behavior-

al design entry and simulation, and is supported by all major

vendors of EDA tools. It allows designers to learn a single

language that is useful for all facets of the design process.

Verilog offers designers the ability to describe designs at many

different levels. At the highest level, designs can be entered

as a description of their behavior. This behavioral description

is not tied to any specific target device. As a result, simulation

• Architecture Explorer™ analysis tool and Dynamic Tim-

• Static Timing Report for all devices

• Source-Level Behavioral Simulation and Debugger

• Testbench Generation

• UltraISR Programming Cable

• Delta39K\Ultra37000 prototype board with a CY37256V

• On-line documentation and help

ing Simulator for PSI, Delta39K and Quantum38K de-

vices:

from Aldec

160-pin TQFP device and a CY39100V 208-pin device

— Graphical waveform simulator

— Graphical entry and modification of all waveforms

— Ability to compare waveforms and highlight differ-

— Ability to probe internal nodes

— Display of inputs, outputs, and high impedance (Z)

— Automatic clock and pulse creation

— Support for buses

— Unlimited simulation time

— Graphical representation of exactly how your design

— Zoom from the device level down to the macrocell

— Determine the timing for any path and view that path

ences before and after a design change

signals in different colors

will be implemented on your specific target device

level

on a graphical representation of the chip

•

San Jose

•

CA 95134

Revised January 9, 2002

•

408-943-2600

CY3138

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