W133 Cypress Semiconductor Corp., W133 Datasheet
W133
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W133 Summary of contents
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... GND 1 GND PCI_F 3V66_0 3V66_1 7 VDDQ3 PCI1:7 GND 3V66_2 3V66_3 VDDQ3 3 SEL133/100# IOAPIC0:2 1 48MHz • 3901 North First Street • San Jose W133 pull-up [1] CPU0:3 (MHz) PCI 133 MHz 33.3 MHz 100 MHz 33.3 MHz 1 56 VDDQ2 2 55 IOAPIC2 3 54 IOAPIC1 4 53 IOAPIC0 X1 ...
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... Split voltage supply signaling provides 2.5V and 3.3V clock frequencies operating up to 133 MHz. From a low-cost 14.31818-MHz reference crystal oscillator, the W133 generates 2.5V clock outputs to support CPUs, core logic chip set, and Direct RDRAM clock generators. It also pro- vides skew-controlled PCI and IOAPIC clocks synchronous to CPU clock, 48-MHz Universal Serial Bus (USB) clock, and rep- licates the 14 ...
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... Figure 2 details the Cypress spreading pattern. Cypress does offer op- tions with more spread and greater EMI reduction. Contact your local Sales representative for details on these devices. EMI Reduction Spread Time Figure 2. Modulation Waveform Profile 3 W133 Non- Spread Spectrum ...
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... Mode Selection Functions The W133 supports the following operating modes controlled through the SEL133/100#, SEL0, and SEL1 inputs. Table 2. Select Functions SEL133/100# SEL1 Table 3. Truth Table SEL 133/100# SEL1 SEL0 CPU HI n 100 MHz ...
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... LOW LOW ON ON LOW LOW ON ON LOW [15, 16] Signal State 0 (disabled) 1 (enabled) 0 (disabled) 1 (enabled) 1 (normal operation) 0 (power down) 5 W133 REF, PCI PCI_F 48MHz OSC. VCOs LOW LOW LOW OFF OFF LOW LOW ...
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... The internal label means inside the chip and is a reference only. This in fact may not be the way that the control is designed. 27. PWRDWN is an asynchronous input and metastable conditions could exist. This signal is required to be synchronized. 28. The shaded sections on the VCO and the Crystal signals indicate an active clock. PRELIMINARY 6 W133 ...
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... Notes: 29. All clock outputs loaded with 6" 60 transmission lines with 20-pF capacitors. 30. W133 logic inputs have internal pull-up devices, except SEL133/100# (pull-ups not CMOS level). PRELIMINARY above those specified in the operating sections of this specifi- cation is not implied. Maximum conditions for extended peri- ods may affect reliability ...
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... DD 32. The W133 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 18 pF; this includes typical stray capacitance of short PCB traces to crystal. 33. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected). ...
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... Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to fre- quency stabilization. Average value during switching transition. Used for determining series termination value. 9 W133 Min. Typ. Max. Unit ...
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... Measured on rising edge at 1.25V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transi- tion. Used for determining series termi- nation value. 10 W133 CPU = 133MHz CPU = 100MHz Min. Typ. Max. Min. Typ. Max. 7.5 7.65 10 10.2 1 ...
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... Measured on rising and falling edge at 1.25V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. Package Type 56-pin SSOP (300 mils) 11 W133 Min Typ Max Unit 16.67 MHz 1 4 ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PRELIMINARY W133 ...