MAX3799 Maxim Integrated Products, MAX3799 Datasheet - Page 13

• Manufacturer Part Number: MAX3799
• Description: SFP+ Multirate Limiting Amplifier And VCSEL Driver
• Manufacturer: Maxim Integrated Products

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(V
default values unless otherwise noted, and the 3-wire interface is static during measurements. For testing, the RATE_SEL bit was
used and the RSEL pin was left open.)
3, 6, 27, 30
12, 15, 18,
CC
21, 24, 25
PIN
= 3.3V, T
10
11
13
1
2
4
5
7
8
9
Typical Operating Characteristics—Limiting Amplifier (continued)
A
1Gbps to 14Gbps, SFP+ Multirate Limiting
= +25°C, unless otherwise specified. Figure 1 shows the typical setup used for measurements. Registers are set to
DISABLE
ROUT+
10
NAME
ROUT-
9
8
7
6
5
4
3
2
RSEL
CSEL
V
V
TIN+
V
LOS
SCL
SDA
CCR
CCD
CCT
-7
______________________________________________________________________________________
PATTERN = PRBS, DATA RATE = 10.32Gbps
-5
vs. PULSE-WIDTH SETTING
DETERMINISTIC JITTER
Loss-of-Signal Output, Open Drain. The default polarity of LOS is high when the level of the input
signal is below the preset threshold set by the SET_LOS DAC. Polarity of the LOS function can be
inverted by setting LOS_POL = 0. The LOS circuitry can be disabled by setting the bit LOS_EN = 0.
Mode-Select Input, TTL/CMOS. Set the RSEL pin or RATE_SEL bit (set by the 3-wire digital interface)
to logic-high for high-bandwidth mode. Setting RSEL and RATE_SEL logic-low for high-gain mode.
The RSEL pin is internally pulled down by a 75k
Power Supply. Provides supply voltage to the receiver block.
Noninverted Receive Data Output, CML. Back-terminated for 50
Inverted Receive Data Output, CML. Back-terminated for 50
Power Supply. Provides supply voltage for the digital block.
Transmitter Disable Input, TTL/CMOS. Set to logic-low for normal operation. Logic-high or open
disables both the modulation and bias current. Internally pulled up by an 8k resistor to V
Serial-Clock Input, TTL/CMOS. This pin has a 75k
Serial-Data Bidirectional Input, TTL/CMOS. Open-drain output. This pin has a 75k
but it requires an external 4.7k pullup resistor to meet the 3-wire digital timing specification. (Data
line collision protection is implemented.)
Chip-Select Input, TTL/CMOS. Setting CSEL to logic-high starts a cycle. Setting CSEL to logic-low
ends the cycle and resets the control state machine. Internally pulled down by a 75k resistor to
ground.
Power Supply. Provides supply voltage to the transmitter block.
Noninverted Transmit Data Input, CML
-3
SET_PWCTRL[3:0]
UP
EYE CROSSING
-1
DOWN
1
3
5
7
Amplifier and VCSEL Driver
FUNCTION
800
700
600
500
400
300
200
100
resistor to ground.
0
internal pulldown.
-40
-25 -10
BIAS MONITOR CURRENT
load.
vs. TEMPERATURE
TEMPERATURE (°C)
5
I
load.
BIAS
I
I
BIAS
BIAS
20
= 12mA
= 8mA
= 2mA
35
Pin Description
50
65
80
internal pullup,
95
CC
.
13