MAX3799 Maxim Integrated Products, MAX3799 Datasheet - Page 14

• Manufacturer Part Number: MAX3799
• Description: SFP+ Multirate Limiting Amplifier And VCSEL Driver
• Manufacturer: Maxim Integrated Products

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1Gbps to 14Gbps, SFP+ Multirate Limiting
Amplifier and VCSEL Driver
The MAX3799 SFP+ transceiver combines a limiting
amplifier receiver with loss-of-signal detection and a
VCSEL laser driver transmitter with fault protection.
Configuration of the advanced Rx and Tx settings of the
MAX3799 is performed by a controller through the
3-wire interface. The MAX3799 provides multiple cur-
rent and voltage DACs to allow the use of low-cost con-
troller ICs.
14
PIN
______________________________________________________________________________________
14
16
17
19
20
22
23
26
28
29
31
32
—
TOUT+
FAULT
NAME
BMON
TOUT-
CAZ2
CAZ1
RIN+
BIAS
V
V
RIN-
TIN-
EP
EER
EET
Detailed Description
Inverted Transmit Data Input, CML
Bias Current Monitor Output. Current out of this pin develops a ground-referenced voltage across an
external resistor that is proportional to the laser bias current.
Ground. Provides ground for the transmitter block.
Inverted Modulation Current Output. Back-termination of 50
Noninverted Modulation Current Output. Back-termination of 50 to V
VCSEL Bias Current Output
Transmitter Fault Output, Open Drain. Logic-high indicates a fault condition. FAULT remains high
even after the fault condition has been removed. A logic-low occurs when the fault condition has
been removed and the fault latch has been cleared by the DISABLE signal.
Ground. Provides ground for the receiver block.
Inverted Receive Data Input, CML
Noninverted Receive Data Input, CML
Offset Correction Loop Capacitor. A capacitor connected between this pin and CAZ1 sets the time
constant of the offset correction loop. The offset correction can be disabled through the digital
interface by setting the bit AZ_EN = 0.
Offset Correction Loop Capacitor. Counterpart to CAZ2, internally connected to V
Exposed Pad. Ground. Must be soldered to circuit board ground for proper thermal and electrical
performance (see the Exposed-Pad Package section).
The limiting amplifier receiver inside the MAX3799 is
designed to operate from 1.0625Gbps to 10.32Gbps.
The receiver includes a dual path limiter, offset correc-
tion circuitry, CML output stage with deemphasis, and
loss-of-signal circuitry. The functions of the receiver can
be controlled through the on-chip 3-wire interface. The
registers that control the receiver functionality are
RXCTRL1, RXCTRL2, RXSTAT, MODECTRL, SET_CML,
and SET_LOS.
FUNCTION
Pin Description (continued)
to V
Limiting Amplifier Receiver
CCT
.
CCT
.
EER
.