WM8971L Wolfson Microelectronics Ltd., WM8971L Datasheet - Page 13

• Manufacturer Part Number: WM8971L
• Description: Stereo Codec for Portable Audio Applications
• Manufacturer: Wolfson Microelectronics Ltd.

Production Data
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SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING
AUDIO INTERFACE TIMING – MASTER MODE
Test Conditions
CLKDIV2=0, DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, T
unless otherwise stated.
PARAMETER
System Clock Timing Information
MCLK System clock pulse width high
MCLK System clock pulse width low
MCLK System clock cycle time
MCLK duty cycle
Test Conditions
CLKDIV2=1, DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, T
unless otherwise stated.
PARAMETER
System Clock Timing Information
MCLK System clock pulse width high
MCLK System clock pulse width low
MCLK System clock cycle time
Figure 1 System Clock Timing Requirements
Figure 2 Digital Audio Data Timing – Master Mode (see Control Interface)
MCLK
(Outputs)
ADCLRC/
DACLRC
ADCDAT
DACDAT
(Output)
BCLK
SYMBOL
SYMBOL
T
T
T
T
T
T
T
MCLKDS
t
MCLKH
MCLKH
DST
MCLKL
MCLKY
MCLKL
MCLKY
A
A
t
MCLKL
= +25
= +25
t
t
MCLKY
DHT
o
o
t
C, Slave Mode fs = 48kHz, MCLK = 384fs, 24-bit data,
C, Slave Mode fs = 48kHz, MCLK = 384fs, 24-bit data,
MCLKH
t
DL
t
DDA
60:40
MIN
MIN
21
21
54
10
10
27
TYP
TYP
PD Rev 4.1 August 2005
40:60
MAX
MAX
WM8971L
UNIT
UNIT
ns
ns
ns
ns
ns
ns
13