WM8971L Wolfson Microelectronics Ltd., WM8971L Datasheet - Page 14

• Manufacturer Part Number: WM8971L
• Description: Stereo Codec for Portable Audio Applications
• Manufacturer: Wolfson Microelectronics Ltd.

WM8971L
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AUDIO INTERFACE TIMING – SLAVE MODE
Note:
BCLK period should always be greater than or equal to MCLK period.
Test Conditions
DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, T
otherwise stated.
PARAMETER
Bit Clock Timing Information
BCLK rise time (10pF load)
BCLK fall time (10pF load)
BCLK duty cycle (normal mode, BCLK = MCLK/n)
BCLK duty cycle (USB mode, BCLK = MCLK)
Audio Data Input Timing Information
ADCLRC/DACLRC propagation delay from BCLK falling edge
ADCDAT propagation delay from BCLK falling edge
DACDAT setup time to BCLK rising edge
DACDAT hold time from BCLK rising edge
Test Conditions
DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, T
otherwise stated.
PARAMETER
Audio Data Input Timing Information
BCLK cycle time
BCLK pulse width high
BCLK pulse width low
ADCLRC/DACLRC set-up time to BCLK rising edge
ADCLRC/DACLRC hold time from BCLK rising edge
DACDAT hold time from BCLK rising edge
ADCDAT propagation delay from BCLK falling edge
Figure 3 Bit Clock Mode
Figure 4 Digital Audio Data Timing – Slave Mode
DACLRC/
ADCDAT
ADCLRC
DACDAT
BCLK
A
A
t
BCH
= +25
= +25
t
BCY
t
o
o
DD
C, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless
C, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless
t
BCL
t
DS
SYMBOL
SYMBOL
t
t
t
t
LRSU
t
t
t
BCH
t
t
BCY
BCL
LRH
t
t
BCLKDS
BCLKDS
DH
DD
BCLKR
BCLKF
t
t
t
t
DDA
DST
DHT
DL
t
LRH
t
DH
t
LRSU
MIN
MIN
10
10
50
20
20
10
10
10
T
50:50
MCLKDS
TYP
TYP
PD Rev 4.1 August 2005
MAX
MAX
10
10
10
3
3
Production Data
UNIT
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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