MAX6900 Maxim, MAX6900 Datasheet - Page 12

• Manufacturer Part Number: MAX6900
• Description: I2C-Compatible RTC in a TDFN
• Manufacturer: Maxim

I
of the Burst Read function. The seven timekeeping reg-
isters are latched upon the receipt of the Burst Read
command. The worst-case error that can occur
between the actual time and the read time is 1s,
assuming the entire Burst Read is done in less than 1s.
The time and date may be set by writing to the timekeep-
ing registers (Seconds, Minutes, Hours, Date, Month,
Day, Year, and Century). To avoid changing the current
time by an incomplete Write operation, the current time
value is buffered from being written directly to the clock
counters. Current time data is loaded into this buffer at
the falling edge of SCL, on the Slave Acknowledge bit,
before the data input byte or bytes are sent to the
MAX6900. The clock counters continue to count. The
new data replaces the current contents of this input
buffer. The time update data is loaded into the clock
counters by the Stop bit at the end of the I
patible Write operation. Collision-detection circuitry
ensures that this does not happen coincident with a sec-
onds counter update to ensure accurate time data is
being written. This avoids time data changes during a
Write operation. An incomplete Write operation aborts
the time update procedure and the contents of the input
buffer are discarded. The clock counters reflect the new
time data beginning with the first 1s clock cycle after the
Stop bit.
When using single Write operations to write to each of
the timekeeping registers, error checking is needed. If
the Seconds register is the one to be updated, update it
first and then read it back and store its value as the ini-
tial seconds. Update the remaining timekeeping regis-
ters and then read the Seconds register again (final
seconds). If initial seconds was 59, ensure that it is still
59. If initial seconds was not 59, ensure that final sec-
onds is within 1s of initial seconds. If the Seconds regis-
ter is not to be written to, then read the Seconds register
first and save it as initial seconds. Write to the required
timekeeping registers and then read the Seconds regis-
ter again (final seconds). If initial seconds was 59,
ensure it is still 59. If initial seconds was not 59, ensure
that final seconds is within 1s of initial seconds.
The burst write mode is the most accurate way to write to
the timekeeping registers, although both single Writes
and Burst Writes are possible. In Burst Write, the main
timekeeping registers (Seconds, Minutes, Hours, Date,
Month, Day, Year) and the control register are written to
sequentially. All the main timekeeping registers and the
Control register must be written to as a group of eight
registers, with 8 bytes each, for proper execution of the
12
2
C-Compatible RTC in a TDFN
______________________________________________________________________________________
Writing to the Timekeeping
2
Registers
C- bus-com-
burst write function. All seven timekeeping registers are
simultaneously loaded into the clock counters by the
Stop bit at the end of the I
ation. The worst-case error that can occur between the
actual time and the write time update is 1s, assuming the
entire Burst Write is done in less than 1s. Note: After
writing to any time or date register, no read or write
operations are allowed for 2.5ms.
Bit 7 of the Control register is the Write Protect bit. The
lower 7 bits (bits 0 to 6) are forced to zero and always
read a zero when read. Before any Write operation to
the clock or RAM, bit 7 must be zero. When high, the
Write Protect bit prevents a Write operation to any other
register.
Bit 7 of the Hours register is defined as the 12hr or 24hr
Mode Select bit. When high, the 12hr mode is selected.
In the 12hr mode, bit 5 is the AM/PM bit with logic high
being PM. In the 24hr mode, bit 5 is the second 10hr
bit (20hr to 23hr).
Addressing the Clock Burst register (BEh for write, or
BFh for read) specifies burst mode operation. In this
mode, the first eight clock/calendar registers can be
consecutively read or written starting with bit 7 of
Address/Command 81h (Read) or 80h (Write). If the
Write Protect bit is set high when a write clock/calendar
burst mode is specified, no data transfer occurs to any
of the eight clock/calendar registers or the Control reg-
ister. When writing to the clock registers in the burst
mode, the first eight registers must be written in order
for the data to be transferred.
The static RAM is 31 bytes addressed consecutively in
the RAM address space. Even Address/Commands
(C0h–FCh) are used for Writes, and odd Address/
Commands (C1h–FDh) are used for Reads. The con-
tents of the RAM are static and remain valid for V
down to 2V.
Addressing the RAM Burst register (FEh for Write, or
FFh for Read) specifies burst mode operation. In this
mode, the 31 RAM locations can be consecutively read
or written starting with bit 7 of Address/Command C1h
(Read) or C0h (Write). When writing to RAM in burst
mode, it is not necessary to write all 31 bytes for the
data to transfer. Each byte that is written to is trans-
ferred to RAM. If the Write Protect bit is set high when a
AM-PM/12Hr-24Hr Mode
2
C-bus-compatible Write oper-
Clock Burst Mode
Write Protect Bit
RAM Burst Mode
RAM
CC