ADS7808 Burr-Brown Corporation, ADS7808 Datasheet - Page 4

• Manufacturer Part Number: ADS7808
• Description: 12-Bit 10ms Serial CMOS Sampling ANALOG-to-DIGITAL CONVERTER
• Manufacturer: Burr-Brown Corporation

PIN ASSIGNMENTS
PIN CONFIGURATION
PIN #
10
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
8
9
DATACLK
EXT/INT
SB/BTC
AGND1
AGND2
PWRD
NAME
DGND
SYNC
DATA
BUSY
V
R1
R2
R3
CAP
REF
TAG
V
R/C
CS
EXT/INT
SB/BTC
ANA
DIG
AGND1
AGND2
DGND
IN
IN
IN
®
CAP
R1
R2
R3
REF
IN
IN
IN
ADS7808
DESCRIPTION
Analog Input. See Table I and Figure 4 for input range connections.
Analog Ground. Used internally as ground reference point. Minimal current flow.
Analog Input. See Table I and Figure 4 for input range connections.
Analog Input. See Table I and Figure 4 for input range connections.
Reference Buffer Capacitor. 2.2 F Tantalum to ground.
Reference Input/Output. Outputs internal 2.5V reference. Can also be driven by external system reference. In both cases,
bypass to ground with a 2.2 F Tantalum capacitor.
Analog Ground.
Select Straight Binary or Binary Two’s Complement data output format. If HIGH, data will be output in a Straight Binary format. If
LOW, data will be output in a Binary Two’s complement format.
Select External or Internal Clock for transmitting data. If HIGH, data will be output synchronized to the clock input on DATACLK. If
LOW, a convert command will initiate the transmission of the data from the previous conversion, along with 12 clock pulses output
on DATACLK.
Digital Ground.
Synch Output. If EXT/INT is HIGH, either a rising edge on R/C with CS LOW or a falling edge on CS with R/C HIGH will output a
pulse on SYNC synchronized to the external DATACLK.
Either an input or an output depending on the EXT/INT level. Output data will be synchronized to this clock. If EXT/INT is LOW,
DATACLK will transmit 12 pulses after each conversion, and then remain LOW between conversions.
Serial Data Output. Data will be synchronized to DATACLK, with the format determined by the level of SB/BTC. In the external clock
mode, after 12-bits of data, the ADS7808 will output the level input on TAG as long as CS is LOW and R/C is HIGH (see Figure 3.) If
EXT/INT is LOW, data will be valid on both the rising and falling edges of DATACLK, and between conversions DATA will stay at the
level of the TAG input when the conversion was started.
Tag Input for use in external clock mode. If EXT/INT is HIGH, digital data input on TAG will be output on DATA with a delay of 12
DATACLK pulses as long as CS is LOW and R/C is HIGH. See Figure 3.
Read/Convert Input. With CS LOW, a falling edge on R/C puts the internal sample/hold into the hold state and starts a conversion.
When EXT/INT is LOW, this also initiates the transmission of the data results from the previous conversion. If EXT/INT is HIGH, a
rising edge on R/C with CS LOW, or a falling edge on CS with R/C HIGH, transmits a pulse on SYNC and initiates the transmission of
data from the previous conversion.
Chip Select. Internally OR’ed with R/C.
Busy Output. Falls when a conversion is started, and remains LOW until the conversion is completed and the data is latched into the
output shift register. CS or R/C must be HIGH when BUSY rises, or another conversion will start without time for signal acquisition.
Power Down Input. If HIGH, conversions are inhibited and power consumption is significantly reduced. Results from the previous
conversion are maintained in the output shift register.
Analog Supply Input. Nominally +5V. Connect directly to pin 20, and decouple to ground with 0.1 F ceramic and 10 F Tantalum
capacitors.
Digital Supply Input. Nominally +5V. Connect directly to pin 19. Must be
10
1
2
3
4
5
6
7
8
9
ADS7808
20
19
18
17
16
15
14
13
12
11
V
V
PWRD
BUSY
CS
R/C
TAG
DATA
DATACLK
SYNC
DIG
ANA
4
TABLE I. Input Range Connections. See Figure 4 for
0V to 10V
ANALOG
0V to 5V
0V to 4V
RANGE
INPUT
3.33
10V
5V
CONNECT R1
V
ANA
VIA 200
complete information.
AGND
AGND
AGND
V
V
V
TO
.
IN
IN
IN
IN
CONNECT R2
VIA 100
AGND
AGND
AGND
V
V
V
TO
IN
IN
IN
IN
CONNECT R3
AGND
CAP
CAP
CAP
V
V
TO
IN
IN
IN
IMPEDANCE
22.9k
13.3k
10.7k
13.3k
10.0k
10.7k