ADS7862YB Burr-Brown Corporation, ADS7862YB Datasheet - Page 11

• Manufacturer Part Number: ADS7862YB
• Description: Dual 500kHz/ 12-Bit/ 2 2 Channel Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTER
• Manufacturer: Burr-Brown Corporation

mode. Figure 9, in conjunction with Table I, shows the basic
read/write functions of the ADS7862 and highlights all of
the timing specifications. Figure 10 shows a more detailed
description of initiating a conversion using CONVST. Fig-
ure 11 illustrates three consecutive conversions and, with the
accompanying text, describes all of the read and write
capabilities of the ADS7862.
NOTES: (1) –V
sponds to a 0V to 5V input span. (2) 1.22mV with a 2.5V reference.
TABLE I. Ideal Input Voltages and Output Codes.
The Figure 11 timing diagram can be divided into three
sections: (a) initiating a conversion (n – 2), (b) starting a
second conversion (n – 1) while reading the data output from
the previous conversion (n – 2), and (c) starting a third
conversion (n) while reading both previous conversions
(n – 2 and n – 1). In this sequence, Channel 0 is converted
FIGURE 9. Reading and Writing to the ADS7862 During the Same Cycle.
DESCRIPTION
Full-Scale Input Span
Least Significant
Bit (LSB)
+Full Scale
Midscale
Midscale – 1 LSB
–Full Scale
CONVST
CLOCK
BUSY
DATA
CS
RD
A0
REF
to +V
(–V
t
t
11
REF
12
ANALOG INPUT
–V
REF
t
3
REF
to +V
4.99878V
2.49878V
t
around V
1
13
2.5V
to +V
0V
REF
REF
)/4096
Conversion n – 1 Results
CHA1
2
t
4
(1)
t
REF
1
t
(2)
5
. With a 2.5V reference, this corre-
3
Conversion n
BINARY TWO’S COMPLEMENT
0111 1111 1111
0000 0000 0000
1111 1111 1111
1000 0000 0000
BINARY CODE
t
CONV
4
CHB1
DIGITAL OUTPUT
5
t
t
2
6
HEX CODE
7FF
000
FFF
800
t
9
14
15
11
t
t
8
ACQ
TIMING SPECIFICATIONS
first followed by Channel 1. Channel 1 can be converted
prior to Channel 0 if the user wishes by simply starting the
conversion process with the A0 pin at logic HIGH (Channel
1) followed by logic LOW (Channel 0).
16
SYMBOL
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CONV
ACQ
CKP
CKL
CKH
1
2
3
4
5
6
7
8
9
10
11
12
13
F
R
t
10
1
CONVST LOW Prior to CLOCK Rising Edge
CONVST LOW After CLOCK Rising Edge
CONVST to BUSY Propagation Delay
RD to HI-Z Delay (Bus Relinquish)
Time Between Conversion Reads
CHA0
RD to Valid Data (Bus Access)
2
Conversion n Results
CS to RD Setup Time
CS to RD Hold Time
t
Address Setup Time
7
Address Hold Time
Conversion Time
Acquisition Time
RD Pulse Width
CONVST HIGH
Data Rise Time
DESCRIPTION
CONVST LOW
Data Fall Time
Clock Period
3
Clock HIGH
Clock LOW
Conversion n + 1
4
CHB0
5
ADS7862
MIN
125
250
40
40
15
30
40
20
20
10
0
0
5
14
TYP
16
10
13
20
15
MAX
5000
1.75
0.25
25
20
30
25
30
16
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
s
®