ADS7862YB Burr-Brown Corporation, ADS7862YB Datasheet - Page 12

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ADS7862YB

Manufacturer Part Number
ADS7862YB
Description
Dual 500kHz/ 12-Bit/ 2 2 Channel Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTER
Manufacturer
Burr-Brown Corporation
Datasheet

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FIGURE 10. Timing Between CLOCK and CONVST to Start a Conversion.
FIGURE 11. ADS7862 Timing Diagram Showing Complete Functionality.
CONVST
CLOCK
DATA
BUSY
TIME 0
RD
CS
A0
1
A0 = 0 Conversion of Ch0
Low Data Level Tri-state of Output
®
ADS7862
NOTE: All CONVST commands which occur more than 10ns before the rising edge of cycle ‘1’ of the external clock
(Region ‘A’) will initiate a conversion on the rising edge of cycle ‘1’. All CONVST commands which occur 5ns after
the rising edge of cycle ‘1’ or 10ns before the rising edge of cycle 2 (Region ‘B’) will initiate a conversion on the
rising edge of cycle ‘2’. All CONVST commands which occur 5ns after the rising edge of cycle ‘2’ (Region ‘C’) will
initiate a conversion on the rising edge of the next clock period. The CONVST pin should never be switched from
HIGH to LOW in the region 10ns prior to the rising edge of the CLOCK and 5ns after the rising edge (gray areas). If
CONVST is toggled in this gray area, the conversion could begin on either the same rising edge of the CLOCK or
the following edge.
Conversion of Ch0
1st RD After CONVST ChA at Output
SECTION A
CONVST
1
CLOCK
min 250ns
10ns
A
2
16
1
A0 = 1 Conversion of Ch1
ChA0 ChB0
Time (seconds)
Cycle 1
125ns
5ns
12
2nd RD After CONVST ChB at Output
Conversion of Ch1
t
CKP
CS Needed Only During Reading
B
SECTION B
High Data Level Output Active
3
Cycle 2
min 250ns
10ns
5ns
C
16
4
1
ChA1
A0 = 0 Conversion of Ch0
Conversion of Ch0
SECTION C
ChB1
A0 Selects Between
Ch0 and Ch1 at Output
ChA0
ChB0
5
Data of Ch0 Still Stored
4 Output-Register

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