ADSP-2171 Analog Devices, ADSP-2171 Datasheet - Page 5

• Manufacturer Part Number: ADSP-2171
• Description: ADSP-2100 Family DSP Microcomputers
• Manufacturer: Analog Devices

REV. A
Interrupts
The interrupt controller allows the processor to respond to the
eleven possible interrupts and reset with minimum overhead.
The ADSP-217x provides up to three external interrupt input
pins, IRQ0, IRQ1 and IRQ2. IRQ2 is always available as a dedi-
cated pin; SPORT1 may be reconfigured for IRQ0, IRQ1, and
the flags. The ADSP-217x also supports internal interrupts from
the timer, the host interface port, the two serial ports, software,
and the powerdown control circuit. The interrupt levels are in-
ternally prioritized and individually maskable (except power-
down and reset). The input pins can be programmed to be
either level- or edge-sensitive. The priorities and vector ad-
dresses of all interrupts are shown in Table II, and the interrupt
registers are shown in Figure 2.
Interrupts can be masked or unmasked with the IMASK regis-
ter. Individual interrupt requests are logically ANDed with the
bits in IMASK; the highest priority unmasked interrupt is then
selected.The powerdown interrupt is nonmaskable.
The ADSP-217x masks all interrupts for one instruction cycle
following the execution of an instruction that modifies the
IMASK register. This does not affect autobuffering.
The interrupt control register, ICNTL, allows the external in-
terrupts to be either edge- or level-sensitive. Interrupt routines
can either be nested with higher priority interrupts taking prece-
dence or processed sequentially.
The IFC register is a write-only register used to force and clear
interrupts generated from software.
4
3
0
ICNTL
2
SPORT1 Transmit or IRQ1
SPORT1 Receive or IRQ0
1
0
INTERRUPT FORCE
SPORT0 Transmit
SPORT0 Receive
IRQ0 Sensitivity
IRQ1 Sensitivity
IRQ2 Sensitivity
Interrupt Nesting
1 = enable, 0 = disable
Software 1
Software 0
Timer
IRQ2
15
0
1 = edge
0 = level
14
0
13
0
12
0
Figure 2. Interrupt Registers
11
15
0
0
SPORT0 Transmit
10
0
14
SPORT0 Receive
0
0
13
0
9
HIP Write
HIP Read
12
0
0
8
–5–
IFC
IRQ2
11
0
0
7
Source of Interrupt
Reset (or Power-Up with PUCR = 1) 0000 (Highest Priority)
Powerdown (Nonmaskable)
IRQ2
HIP Write
HIP Read
SPORT0 Transmit
SPORT0 Receive
Software Interrupt 1
Software Interrupt 0
SPORT1 Transmit or IRQ1
SPORT1 Receive or IRQ0
Timer
On-chip stacks preserve the processor status and are automati-
cally maintained during interrupt handling.
The stacks are twelve levels deep to allow interrupt nesting.
The following instructions allow global enable or disable servic-
ing of the interrupts (including powerdown), regardless of the
state of IMASK. Disabling the interrupts does not affect
autobuffering.
ENA INTS;
DIS INTS;
When you reset the processor, the interrupt servicing is enabled.
10
0
0
6
Table II. Interrupt Priority & Interrupt Vector Addresses
0
ADSP-2171/ADSP-2172/ADSP-2173
0
5
9
0
8
0
4
IMASK
0
7
0
3
0
6
0
2
0
5
0
1
0
4
0
0
0
3
Timer
SPORT1 Receive or IRQ0
SPORT1 Transmit or IRQ1
Software 0
Software 1
SPORT0 Receive
SPORT0 Transmit
IRQ2
INTERRUPT CLEAR
2
0
0
1
0
0
1 = enable, 0 = disable
Timer
IRQ0 or SPORT1 Receive
IRQ1 or SPORT1 Transmit
Software 0
Software 1
Interrupt Vector
Address (Hex)
002C
0004
0008
000C
0010
0014
0018
001C
0020
0024
0028 (Lowest Priority)