ADSP-2187L Analog Devices, ADSP-2187L Datasheet - Page 19

• Manufacturer Part Number: ADSP-2187L
• Description: DSP Microcomputer
• Manufacturer: Analog Devices

TIMING PARAMETERS
Parameter
Clock Signals and Reset
Timing Requirements:
t
t
t
Switching Characteristics:
t
t
t
Control Signals
Timing Requirement:
t
t
t
NOTE
1
REV. 0
Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal
CKI
CKIL
CKIH
CKL
CKH
CKOH
RSP
MS
MH
oscillator start-up time).
CLKIN External Clock Period
CLKIN Width Low
CLKIN Width High
CLKOUT Width Low
CLKOUT Width High
CLKIN High to CLKOUT High
RESET Width Low
Mode Setup before RESET High
Mode Hold after RESET High
CLKOUT
PF(3:0)
RESET
CLKIN
(See page 16, Frequency Depending for Timing Specifications, for timing definitions.)
*
*
PF3 IS MODE D, PF2 IS MODE C, PF1 IS MODE B, PF0 IS MODE A
Figure 20. Clock Signals
t
CKIL
t
CKI
t
MS
t
CKL
–19–
t
MH
0
5t
Min
38
15
15
0.5t
0.5t
2
5
t
CKOH
CK
t
CKH
CK
CK
1
t
CKIH
– 7
– 7
Max
100
20
ADSP-2187L
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit