ADSP-2187L Analog Devices, ADSP-2187L Datasheet - Page 4

• Manufacturer Part Number: ADSP-2187L
• Description: DSP Microcomputer
• Manufacturer: Analog Devices

ADSP-2187L
Common-Mode Pin Descriptions
Pin
Name(s)
RESET
BR
BG
BGH
DMS
PMS
IOMS
BMS
CMS
RD
WR
IRQ2/
PF7
IRQL0/
PF6
IRQL1/
PF5
IRQE/
PF4
Mode D/
PF3
Mode C/
PF2
Mode B/
PF1
Mode A/
PF0
CLKIN,
XTAL
CLKOUT 1
SPORT0
SPORT1
IRQ1:0
FI, FO
PWD
PWDACK 1
FL0, FL1,
FL2
VDD and
GND
EZ-Port
# of
Pins Output
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
5
5
1
3
16
9
Input/
I
I
O
O
O
O
O
O
O
O
O
I
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
O
I/O
I/O
I
O
O
I
I/O
Programmable I/O Pin
Programmable I/O Pin
Programmable I/O Pin
Programmable I/O Pin During
Programmable I/O Pin During
Programmable I/O Pin During
Programmable I/O Pin During
Clock or Quartz Crystal Input
Processor Clock Output
Serial Port I/O Pins
Serial Port I/O Pins
Output Flags
For Emulation Use
Function
Processor Reset Input
Bus Request Input
Bus Grant Output
Bus Grant Hung Output
Data Memory Select Output
Program Memory Select Output
Memory Select Output
Byte Memory Select Output
Combined Memory Select Output
Memory Read Enable Output
Memory Write Enable Output
Edge- or Level-Sensitive Interrupt
Request.
Level-Sensitive Interrupt Requests
Level-Sensitive Interrupt Requests
Edge-Sensitive Interrupt Requests
Mode Select Input—Checked
Only During RESET
Normal Operation
Mode Select Input—Checked
Only During RESET
Normal Operation
Mode Select Input—Checked
Only During RESET
Normal Operation
Mode Select Input—Checked
Only During RESET
Normal Operation
Edge- or Level-Sensitive Interrupts,
Flag In, Flag Out
Power-Down Control Input
Power-Down Control Output
Power and Ground
1
Programmable I/O Pin
2
1
1
1
–4–
NOTES
1
2
Memory Interface Pins
The ADSP-2187L processor can be used in one of two modes,
Full Memory Mode, which allows BDMA operation with full
external overlay memory and I/O capability, or Host Mode,
which allows IDMA operation with limited external addressing
capabilities. The operating mode is determined by the state of
the Mode C pin during RESET and cannot be changed while
the processor is running. See tables for Full Memory Mode Pins
and Host Mode Pins for descriptions.
Full Memory Mode Pins (Mode C = 0)
Pin
Name(s) Pins Output Function
A13:0
D23:0
Host Mode Pins (Mode C = 1)
Pin
Name(s) Pins Output Function
IAD15:0 16
A0
D23:8
IWR
IRD
IAL
IS
IACK
In Host Mode, external peripheral addresses can be decoded using the A0,
CMS, PMS, DMS and IOMS signals
Terminating Unused Pin
The following table shows the recommendations for terminating
unused pins.
Pin Terminations
Pin
Name
XTAL
CLKOUT
A13:1 or
IAD12:0
A0
D23:8
D7 or
IWR
Interrupt/Flag Pins retain both functions concurrently. If IMASK is set to en-
SPORT configuration determined by the DSP System Control Register. Soft-
able the corresponding interrupts, then the DSP will vector to the appropriate
interrupt vector address when the pin is asserted, either by external devices, or
set as a programmable flag.
ware configurable.
# of
14
24
# of
1
16
1
1
1
1
1
I/O
3-State
(Z)
I
O
O (Z)
I/O (Z)
O (Z)
I/O (Z)
I/O (Z)
I
Input/
O
I/O
Input/
I/O
O
I/O
I
I
I
I
O
Reset
State
I
O
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
I
Address Output Pins for Program,
Data, Byte and I/O Spaces
Data I/O Pins for Program, Data,
Byte and I/O Spaces (8 MSBs are
also used as Byte Memory addresses)
IDMA Port Address/Data Bus
Address Pin for External I/O, Pro-
gram, Data or Byte access
Data I/O Pins for Program, Data
Byte and I/O spaces
IDMA Write Enable
IDMA Read Enable
IDMA Address Latch Pin
IDMA Select
IDMA Port Acknowledge Configur-
able in Mode D; Open Source
Hi-Z*
Caused
By
BR, EBR Float
IS
BR, EBR Float
BR, EBR Float
BR, EBR Float
Unused
Configuration
Float
Float
High (Inactive)
Float
REV. 0