SC486 Semtech Corporation, SC486 Datasheet - Page 19

• Manufacturer Part Number: SC486
• Description: Complete DDR1/2/3 Memory Power Supply
• Manufacturer: Semtech Corporation

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Layout Guidelines
One (or more) ground planes is/are recommended to minimize the effect of switching noise and copper losses, and
maximize heat dissipation. The IC ground reference, VSSA, should be connected to PGND1 and PGND2 as a star
connection at the thermal pad, which in turn is connected using 4 vias to the ground plane. All components that are
referenced to VSSA should connect to it directly on the chip side, and not through the ground plane.
VDDQ: the feedback trace must be kept far away from noise sources such as switching nodes, inductors and gate
drives. Route the feedback trace in a quiet layer if possible from the output capacitor back to the chip.
Chip supply decoupling capacitors (VCCA, VDDP) should be located next to the pins (VCCA and VSSA, VDDP and
PGND1) and connected directly to them on the same side.
VTT: output capacitors should be located right across the VTT output pins (VTT and PGND2) as close as possible to
the part to minimize parasitics.
The switcher power section should connect directly to the ground plane(s) using multiple vias as required for current
handling (including the chip power ground connections). Power components should be placed to minimize loops and
reduce losses. Make all the connections on one side of the PCB using wide copper filled areas if possible. Do not
use “minimum” land patterns for power components. Minimize trace lengths between the gate drivers and the
gates of the MOSFETs to reduce parasitic impedances (and MOSFET switching losses), the low-side MOSFET is most
critical. Maintain a length to width ratio of <20:1 for gate drive signals. Use multiple vias as required by current
handling requirement (and to reduce parasitics) if routed on more than one layer. Current sense connections must
always be made using Kelvin connections to ensure an accurate signal.
We will examine the SC486 DDR2 reference design used in the Design Procedure section while explaining the layout
guidelines in more detail.
Sample DDR2 Design Using SC486
VBAT = 9V to 19.2V
VDDQ = 1.8V @ (8+2)A
VTT = 0.9V @ 2A
POWER MANAGEMENT
VDDQ
2006 Semtech Corp.
REF
VDDQ
C1
no-pop
VTT
R5 4k64
23k2
R4 10R
R8
C2
1u
R6
10R
C9
1u
R7 10R
Figure 4: DDR2 Reference Design and Layout Example
C10
no-pop
C15
10u
R9 0R
C3
no-pop
C16
10u
VBAT
R1
715k
C11
1n
5VSUS
C17
1u
R2
10R
C12
1u
5VRUN
11
10
14
15
12
13
16
17
3
2
6
8
9
5
4
U1
VTTEN
VDDQS
TON
FB
REF
COMP
VTTS
VCCA
VSSA
VTT
VTT
VTTIN
VTTIN
PGND2
PGND2
19
EN/PSV
PGND1
SC486
VDDP
PGD
ILIM
BST
DH
DL
LX
7
1
24
23
21
22
19
20
18
5VSUS
C18
1u
R10 13k0
D1
C4
0.1uF
R3 470k
Q1
IRF7811AV
Q2
FDS6676S
VBAT
C5
2n2/50V
L1
1u5
C6
0u1/25V
+
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C13
220u/15m
SC486
C7
10u/25V
PGOOD
+
C14
220u/15m
C8
10u/25V
VDDQ