nRF24LE1 Nordic VLSI, nRF24LE1 Datasheet - Page 75

• Manufacturer Part Number: nRF24LE1
• Manufacturer: Nordic VLSI

nRF24LE1 Preliminary Product Specification
6.3.2
There is an on-chip brown-out detector that ensures that the write operation is aborted safely and that the
chip restarts from reset if there is a power disturbance during any flash write operation.
6.3.3
This section describes how you can write and erase the flash memory using the MCU.
6.3.3.1
When a flash write is initiated, the MCU is halted for 740 clock cycles (46µs @16Mhz) for each byte writ-
ten. When a page erase is initiated, the MCU can be halted for up to 360,000 clock cycles (22.5 ms
@16Mhz). During this time the MCU does not respond to any interrupts. Firmware must assure that page
erase does not interfere with normal operation of the nRF24LE1.
The MCU can perform erase page and write operations to the unprotected part and the data part of the
flash main block. To prevent unwanted/harmful erase and write operations a MCU write protect security
mechanism is implemented.
To allow erase and write flash operations the MCU must run the following sequence:
Revision 1.1
Address
1.
2.
3.
4.
(hex)
0xFA
0xF9
a. Can only be written indirectly through InfoPage, by dedicated SPI command, and is ignored by WRSR
command.
Set WEN (bit 5) in the FSR register high to enable flash erase/write access. The flash is now open
Before updating the flash memory it must be erased. Erase operations can only be performed on
Set PMW (bit 4) in the PCON register high to enable program memory write mode.
Programming the flash is done through normal memory write operations from the MCU. Bytes are
for erase and write from the MCU until WEN in FSR is set low again.
whole pages. To erase a page, write page address (range 0-31) to the FCR register.
written individually (there is no auto increment) to the flash using the specific memory address.
Mnemonic
Brown-out
Flash programming from the MCU
FPCR
NUPP
FCR
Flash com-
mand regis-
ter
MCU write and erase operations in the main block
Table 31. Registers for MCU and SPI for FLASH configuration control
Bit
6:0
7:0
0
7
Reset
value
0
1
0
access
SPI
R
R
R
75 of 191
-
access
SFR
R/W Reserved
R/W A (SFR) write to this register erases the
R
R
Flash Protect Config Register
Reserved
Number of unprotected pages.
NUPP will contain the page address of the
first protected page if used. Note that this
setting (36>NUPP>=0) reserves the 16
highest bytes of the main block, regardless
of other settings. FDCR must be set < 36 in
order to update page 35
Flash Command Register
page with address equal to the register
value, if value is < 36. (max page address).
Addresses 33-35 will erase data pages.
Description