HY27UF081G2M Hynix Semiconductor, HY27UF081G2M Datasheet
HY27UF081G2M
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HY27UF081G2M Summary of contents
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Document Title 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory Revision History Revision No. 0.0 1) Initial Draft. 1) Correct Fig.10 Sequential out cycle after read 2) Add the text to Fig.1, Table.1, Table.2 - text : IO15 - IO8 (x16 ...
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Revision History Revision No. 1) Correct AC characteristics(tREH) before: 30ns-> after: 20ns 2) Add Errata 0.5 Specification Read(all) Relaxed Except for value ID Read ID Read 1) Change AC characteristics Before 0.6 After 2) Add tADL parameter - tADL=100ns 3) ...
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FEATURES SUMMARY HIGH DENSITY NAND FLASH MEMORIES - Cost effective solutions for mass storage applications NAND INTERFACE - x8 or x16 bus width. - Multiplexed Address/ Data - Pinout compatibility for all densities SUPPLY VOLTAGE - 3.3V device: VCC = ...
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... This device includes also extra features like OTP/Unique ID area, Automatic Read at Power Up, Read ID2 extension. The HYNIX HY27(U/S)F(08/16)1G2M series is available TSOP1 WSOP1 mm, FBGA 9 mm. 1.1 Product List PART NUMBER HY27SF081G2M HY27SF161G2M HY27UF081G2M HY27UF161G2M Rev 0.6 / Mar. 2005 HY27UF(08/16)1G2M Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash ORIZATION VCC RANGE x8 1 ...
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IO15 - IO8 IO7 - IO0 CLE ALE CE# RE# WE# WP# RB# Vcc Vss NC PRE Rev 0.6 / Mar. 2005 HY27UF(08/16)1G2M Series HY27SF(08/16)1G2M Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Figure1: Logic Diagram Data Input / Outputs (x16 ...
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Figure 2. 48TSOP1 Contactions, x8 and x16 Device Figure 3. 48WSOP1 Contactions, x8 and x16 Device Rev 0.6 / Mar. 2005 HY27UF(08/16)1G2M Series HY27SF(08/16)1G2M Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Preliminary 6 ...
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Figure 4. 63FBGA Contactions, x8 Device (Top view through package) Figure 5. 63FBGA Contactions, x16 Device (Top view through package) Rev 0.6 / Mar. 2005 HY27UF(08/16)1G2M Series HY27SF(08/16)1G2M Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Preliminary 7 ...
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PIN DESCRIPTION Pin Name DATA INPUTS/OUTPUTS IO0-IO7 The IO pins allow to input command, address and data and to output data during read / program IO8-IO15(1) operations. The inputs are latched on the rising edge of Write Enable (WE#). ...
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IO0 1st Cycle A0 2nd Cycle A8 3rd Cycle A12 4th Cycle A20 IO0 1st Cycle A0 2nd Cycle A8 3rd Cycle A11 4th Cycle A19 FUNCTION READ 1 READ FOR COPY-BACK READ ID RESET PAGE PROGRAM (start) COPY BACK ...
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CLE ALE CE ( NOTE: 1. With ...
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BUS OPERATION There are six standard bus operations that control the device. These are Command Input, Address Input, Data Input, Data Output, Write Protect, and Standby. Typically glitches less than Chip Enable, Write Enable and Read ...
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DEVICE OPERATION 3.1 Page Read. Upon initial device power up, the device defaults to Read mode. This operation is also initiated by writing 00h and 30h to the command register along with four address cycles. In two consecutive read ...
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Block Erase. The Erase operation is done on a block basis. Block address loading is accomplished in two cycles initiated by an Erase Setup command (60h). Only address A18 to A27 (X8) or A17 to A26 (X16) is valid ...
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Read ID. The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. Four read cycles sequentially output the manufacturer code (ADh), and the device code and 00h, ...
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Cache read operation allows automatic download of consecutive pages the whole device. Immediately after 1st latency end, while user can start reading out data, device internally starts reading following page. Start address of 1st page is at page ...
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OTHER FEATURES 4.1 Data Protection. The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 1.5V. WP# pin provides hardware protection and is recommended ...
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Multiple Die (2Gbit / 4Gbit) Concurrent Operations and Extended Read Status When the 1Gbit is stacked to form a 2Gbit DDP or a 4Gbit QDP some concurrent operations (like Erase while Read, Read while write, etc.) are available. Moreover ...
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Symbol Ambient Operating Temperature (Commercial Temperature Range) T Ambient Operating Temperature (Extended Temperature Range) A Ambient Operating Temperature (Industrial Temperature Range) T Temperature Under Bias BIAS T Storage Temperature STG (2) Input or Output Voltage V IO Vcc Supply Voltage ...
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Rev 0.6 / Mar. 2005 HY27UF(08/16)1G2M Series HY27SF(08/16)1G2M Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Figure 6: Block Diagram Preliminary 19 ...
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Parameter Symbol Sequential I CC1 Read Operating Current Program I CC2 Erase I CC3 Stand-by Current (TTL) I CC4 Stand-by Current (CMOS) I CC5 Input Leakage Current I LI Output Leakage Current I LO Input High Voltage V IH Input ...
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Item Input / Output Capacitance (1) Input Capacitance(1) Table 12: Pin Capacitance (TA=25C, F=1.0MHz) Note: 1. For the stacked devices version the Input Capacitance is <TBD> and the I/O capacitance is <TBD> Parameter Program Time Dummy Busy Time for Cache ...
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Parameter CLE Setup time CLE Hold time CE# setup time CE# hold time WE# pulse width ALE setup time ALE hold time Data setup time Data hold time Write Cycle time WE# High hold time ALE to Data Loading time ...
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Pagae Block IO Program Erase 0 Pass / Fail Pass / Fail Ready/Busy Ready/Busy 6 Ready/Busy Ready/Busy 7 Write Protect Write Protect DEVICE IDENTIFIER BYTE 1st 2nd ...
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Description 1K Page Size 2K (Without Spare Area) Reserved Reserved Spare Area Size 8 (Byte / 512Byte) 16 Standard (50ns) Serial Access Time Fast 64K Block Size 128K (Without Spare Area) 256K Reserved X8 Organization X16 Not Used Table 17: ...
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Rev 0.6 / Mar. 2005 HY27UF(08/16)1G2M Series HY27SF(08/16)1G2M Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Figure 8: Address Latch Cycle Preliminary 25 ...
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Figure 10: Sequential Out Cycle after Read (CLE=L, WE#=H, ALE=L) Rev 0.6 / Mar. 2005 HY27UF(08/16)1G2M Series HY27SF(08/16)1G2M Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Figure 9. Input Data Latch Cycle Preliminary 26 ...
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Figure 12: Read1 Operation (Read One Page) Rev 0.6 / Mar. 2005 HY27UF(08/16)1G2M Series HY27SF(08/16)1G2M Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Figure 11: Status Read Cycle Preliminary 27 ...
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Figure 13: Read1 Operation intercepted by CE# Rev 0.6 / Mar. 2005 HY27UF(08/16)1G2M Series HY27SF(08/16)1G2M Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Preliminary 28 ...
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Rev 0.6 / Mar. 2005 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Figure 14 : Random Data output Preliminary HY27UF(08/16)1G2M Series HY27SF(08/16)1G2M Series 29 ...
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Rev 0.6 / Mar. 2005 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Figure 15: Page Program Operation Preliminary HY27UF(08/16)1G2M Series HY27SF(08/16)1G2M Series 30 ...
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Rev 0.6 / Mar. 2005 HY27UF(08/16)1G2M Series HY27SF(08/16)1G2M Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Figure 16 : Random Data In Preliminary 31 ...
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Rev 0.6 / Mar. 2005 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Figure 17 : Copy Back Program Preliminary HY27UF(08/16)1G2M Series HY27SF(08/16)1G2M Series 32 ...
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Rev 0.6 / Mar. 2005 HY27UF(08/16)1G2M Series HY27SF(08/16)1G2M Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Figure 18 : Cache Program Preliminary 33 ...
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Figure 19: Block Erase Operation (Erase One Block) Rev 0.6 / Mar. 2005 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Figure 20: Read ID Operation Preliminary HY27UF(08/16)1G2M Series HY27SF(08/16)1G2M Series 34 ...
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Figure 21: start address at page start :after 1st latency uninterrupted data flow Figure 22: exit from cache read in 5ms when device internally is reading Rev 0.6 / Mar. 2005 HY27UF(08/16)1G2M Series HY27SF(08/16)1G2M Series 1Gbit (128Mx8bit / 64Mx16bit) NAND ...
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Figure 23: Page Read with CE# Don’t Care Option Rev 0.6 / Mar. 2005 HY27UF(08/16)1G2M Series HY27SF(08/16)1G2M Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Preliminary 36 ...
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Rev 0.6 / Mar. 2005 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Figure 24: Automatic Read at Power On Figure 25: Reset Operation Preliminary HY27UF(08/16)1G2M Series HY27SF(08/16)1G2M Series 37 ...
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Figure 26: Power On and Data Protection Timing VTH = 1.5 Volt for 1.8 Volt Supply devices; 2.5 Volt for 3.3 Volt Supply devices * See the Application Note.1 Rev 0.6 / Mar. 2005 HY27UF(08/16)1G2M Series HY27SF(08/16)1G2M Series 1Gbit (128Mx8bit ...
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Figure 27: Ready/Busy Pin electrical specifications Rev 0.6 / Mar. 2005 HY27UF(08/16)1G2M Series HY27SF(08/16)1G2M Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Preliminary 39 ...
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Figure 28: page programming within a block Rev 0.6 / Mar. 2005 HY27UF(08/16)1G2M Series HY27SF(08/16)1G2M Series 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Preliminary 40 ...
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Bad Block Management Devices with Bad Blocks have the same quality level and the same AC and DC characteristics as devices where all the blocks are valid. A Bad Block does not affect the performance of valid blocks because it ...
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APPENDIX : Extra Features 5.1 Automatic Page0 Read after Power Up The timing diagram related to this operation is shown in Fig. 24 Due to this functionality the CPU can directly download the boot loader from the first page ...
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Figure 30. 48-TSOP1 - 48-lead Plastic Thin Small Outline 20mm, Package Outline Symbol alpha Table 19: 48-TSOP1 - 48-lead Plastic Thin Small Outline, Rev 0.6 / Mar. ...
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Figure 31. 48-WSOP1 - 48-lead Plastic Very Very Thin Small Outline, Symbol alpha Table 20: 48-WSOP1- 48-lead Plastic Thin Small Outline, Rev 0.6 / Mar. 2005 1Gbit (128Mx8bit / ...
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Figure 32. FBGA 63 - 9 ball array 0.8mm pitch, Pakage Outline NOTE: Drawing is not to scale. Symbol FD1 FE FE1 SD ...
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Application Note 1. Power-on/off Sequence After power is on, the device starts an internal circuit initialization when the power supply voltage reaches a specific level. The device shows its internal initialization status with the Ready/Busy signal if initialization is on ...
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Automatic sleep mode for low power consumption The device provides the automatic sleep function for low power consumption. The device enters the automatic sleep mode by keeping CE# at VIH level for 10us without any additional command input, and ...