MT9125 Zarlink Semiconductor, MT9125 Datasheet
MT9125
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MT9125 Summary of contents
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This product is obsolete. This information is available for your convenience only. For more information on Zarlink’s obsolete products and replacement product lists, please visit http://products.zarlink.com/obsolete_products/ ...
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... Switching, on-the-fly, between 32 kbit/s and 24 kbit possible by toggling the appropriate Mode Select (MS1-MS4) control pins. PCM I/O IC MS1 MS2 Figure 1 - Functional Block Diagram MT9125 CMOS Dual ADPCM Transcoder Preliminary Information ISSUE 3 August 1993 Ordering Information 24 Pin Plastic DIP (600 mil) ...
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... MT9125 24 PIN PDIP 28 PIN PLCC Pin Description Pin # Name DIP PLCC 1 2 MCLK Master Clock input. This 4.096 MHz clock is used as an internal master clock and must be provided during both ST-BUS and SSI modes of operation. This is a TTL level input. In ST-BUS mode the MCLK input (also known as C4i in ST-BUS terms) is derived from the synchronous 4 ...
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... Description MS1 B1 Channel 0 algorithm reset 1 ADPCM bypass mode ( kbit/ kbit/s ADPCM mode 1 32 kbit/s ADPCM mode MS3 B2 Channel 0 algorithm reset 1 ADPCM bypass mode ( kbit/ kbit/s ADPCM mode 1 32 kbit/s ADPCM mode for normal operation. SS 10%. MT9125 . 8-75 ...
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... MT9125 Pin Description (continued) Pin # Name DIP PLCC 22 26 EN1 Channel 1 Output Enable strobe. This output is decoded from the ST-BUS C4i and F0i signals and its position, within the ST-BUS stream, may be controlled via the ENS pin. Refer to the ST-BUS relative timing diagram shown in Figure 4. ...
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... B1 and B2 channels as defined by respectively. Note that ENB1 and ENB2 are also used as the framing inputs for internal operation of 8 bits B2 Channel 4 bits 4 bits B2 B1 Figure 3 - SSI Mode Relative Timing MT9125 input strobes ENB1 and ENB2, 4 bits B2 8-77 ...
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... MT9125 F0i Channel 0 B1 DSTi/o EN1 EN2 ADPCMi/o EN1 EN2 ADPCMi/o In ST-BUS mode the ENA, ENB1 and ENB2 input strobes are ignored. All timing is dervied internally from the F0i, MCLK and ENS inputs. the device and must, therefore, be present whenever a transcoding operation is required. These inputs may be tied together and connected to the same strobe for single channel operation ...
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... The minimum MCLK period is 190 nSeconds, which translates to a maximum frequency of 5.26 MHz. Extra MCLK cycles (>512/ frame) are acceptable because the transcoder is re- aligned by the appropriate strobe signals each frame. MT9125 DSTo DSTi Dual ADPCM Transcoder B2 ADPCM i ...
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... MT9125 frame n-1 DSTi PCM Byte "X" latched into device during frame n-1 ADPCMo ENA ENB1 or EN1 MS1/3 1,1=32 kb/s MS2/4 This diagram shows the conversion sequence from PCM to ADPCM. The same pipelining occurs in the reverse ADPCM to PCM direction. Total delay from data input to data output = 2 frames. See Figure 15 for detailed ENB1/EN1 timing. ...
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... F0i EN1 MCLK EN2 ADPCMi DSTi ADPCMo DSTo ENA ENB1 ENB2 V DD MT9125 C2o ENS BCLK F0i EN1 MCLK EN2 ADPCMi DSTi ADPCMo DSTo ENA ENB1 ENB2 MT9125 FxL FxL BCLK MCLK FRO ...
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... ST-BUS MT9125 BCLK ENS F0i MCLK ADPCMi DSTi ADPCMo DSTo ENA ENB1 ENB2 V DD MT9125 BCLK ENS F0i MCLK ADPCMi DSTi ADPCMo DSTo ENA ENB1 ENB2 Figure 9 - Pair Gain Application (SSI/SSI) Preliminary Information ...
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... DSTo ADPCMo ENB1 ENA ENB2 ENB2 MT9125 MT8980 B Channel Switch FPib DSTi DSTo FPib DSTo DSTi C4ib FPob 1 DSTo FPib DSTi C4ib FPob 7 FPib DSTo DSTi C4ib FPob 8 BIT CLOCK ADPCM ENABLE ...
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... MT9125 Absolute Maximum Ratings* Parameter 1 Supply Voltage 2 Voltage on any I/O pin 3 Continuous Current on any I/O pin 4 Storage Temperature 5 Power Dissipation 6 Latch-up Immunity * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Recommended Operating Conditions Characteristics 1 Supply Voltage 2 Input High Voltage ...
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... DIH 122 F0iS t 50 122 F0iH x100 t 190 C4P t DSToD t 50 DSTiH t 50 DSTiS MT9125 Max Units Test Conditions ns C =150pF =150pF L 7900 ns C =150pF =150pF =150pF =150pF BCL L 80 ...
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... MT9125 t BCL BCLK t S SSS S ENB1 I or ENB2 b7 DSTi DSTo S MCLK F0iH U S F0i t F0iS t BCL BCLK t S SSS S I ENA b1-1 ADPCMi t SD b1-1 ADPCMo S MCLK F0iH U S F0i t F0iS 8-86 t CLH t CLL t t DIS DIH DSTiS t DSTiH b6 b5 ...
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... D1 t 100 † - Mode Select Timing (see Figure 15) † Sym Min Typ t 500 SU t HOLD HOLD MT9125 Units Test Conditions ns 150pF Load ns 150pF Load Max Units Test Conditions ...
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... MT9125 Notes: 8-88 Preliminary Information ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...