MT9125 Zarlink Semiconductor, MT9125 Datasheet - Page 4

• Manufacturer Part Number: MT9125
• Description: Dual Adpcm Transcoder
• Manufacturer: Zarlink Semiconductor

Preliminary Information
Pin Description (continued)
DIP
10,
12,
11
13
14
15
16
17
18
19
20
21
6
7
8
9
Pin #
PLCC
12,
14,
10
11
13
16
17
18
19
20
22
23
24
25
7
8
ADPCMo Serial ADPCM word output stream. Refer to the serial timing diagram of Fig.13.
FORMAT Format select input. Selects CCITT PCM coding if high, or SIGN MAGNITUDE PCM if low.
PWRDN Power Down input. Logic low on this pin forces the device to assume an internal power
ADPCMi Serial ADPCM word input data stream. Refer to the serial timing diagram of Fig. 13. This is
Name
BCLK
ENB2
ENB1
MS1,
MS3,
MS2
MS4
ENA
V
V
A/
IC
DD
SS
Bit Clock input for both PCM and ADPCM ports; used in SSI mode only. The falling edge of
this clock is used to clock data in on DSTi and ADPCMi. The rising edge is used to clock
data out on DSTo and ADPCMo. Can be any rate between 128 kHz and 2.048 MHz. Refer
to the serial timing diagrams of Figures 12 and 13. When not used, this pin should be tied
to V
This is a TTL level input.
Power supply ground (0 volts).
Enable Strobe input for B2 channel PCM timing in SSI mode only. A valid 8-bit strobe must
be present at this input if there are no ST-BUS signals at F0i and MCLK. When the device
detects a valid frame pulse at F0i, PCM timing for the B2 ST-BUS channel is decoded
internally and the ENB2 input is ignored. When not used this pin should be tied to V
This is a TTL level input.
Enable Strobe input for B1 channel PCM timing in SSI mode only. A valid 8-bit strobe must
be present at this input if there are no ST-BUS signals at F0i and MCLK. When the device
detects a valid frame pulse at F0i, PCM timing for the B1 ST-BUS channel is decoded
internally and the ENB1 input is ignored. When not used this pin should be tied to V
This is a TTL level input.
Mode select control input pins 1 and 2 for the B1 channel according to the following:
These are TTL level inputs.
Mode select control input pins 3 and 4 for the B2 channel according to the following:
These are TTL level inputs.
Law select input. Selects -Law when low, A-Law when high.
This is a TTL level input.
This is a TTL level input.
down mode where all operation is halted. This mode minimizes power consumption.
Outputs are tri-stated. This is a schmidt trigger input.
Internal Connection. Tie to V
Positive power supply input, 5 volts
Enable Strobe input for both input and output ADPCM channels; used for SSI operation
only. Refer to Figure 3. When not used, tie to VSS.
This is a TTL level input.
a TTL level input.
SS
.
MS2
MS4
0
0
1
1
0
0
1
1
MS1
MS3
0
1
0
1
0
1
0
1
SS
B1 Channel
algorithm reset
ADPCM bypass mode (24 or 32 kbit/s)
24 kbit/s ADPCM mode
32 kbit/s ADPCM mode
B2 Channel
algorithm reset
ADPCM bypass mode (24 or 32 kbit/s)
24 kbit/s ADPCM mode
32 kbit/s ADPCM mode
for normal operation.
10%.
Description
MT9125
SS
SS
.
.
8-75