MT9160BE Zarlink Semiconductor, MT9160BE Datasheet
MT9160BE
Related parts for MT9160BE
MT9160BE Summary of contents
Page 1
... Flexible Digital STB/F0i Interface CLOCKin STBd/FOod (MT9161B only) ISO 5 Volt Multi-Featured Codec (MFC) DS5145 MT9161BE MT9160BE MT9161BS MT9160BS MT9161BN MT9160BN Description The MT9160B/61B incorporates a built-in Filter/Codec, gain control and programmable sidetone path as well as on-chip anti-alias filters, reference voltage and bias source. ...
Page 2
... D Data Input. A digital input for 8 bit wide channel data received from the Layer 1 in transceiver. Data is sampled on the falling edge of the bit clock during the timeslot defined by STB, or according to standard ST-BUS timing. Input level is CMOS compatible. 80 MT9160BE VBias VRef 2 23 ...
Page 3
Advance Information Pin Description (continued) Pin # Pin # Name 20 Pin 24 Pin 13 15 STB/F0i Data Strobe/Frame Pulse (Input). For SSI mode this input determines the 8 bit timeslot used by the device for both transmit and receive ...
Page 4
MT9160B/61B In the event of PWRST, the MT9160B/61B defaults such that the side-tone path is off, all programmable gains are set to 0dB and ITU-T -Law is selected. Further, the digital port is set to SSI mode operation at 2048 ...
Page 5
Advance Information Filter/Codec and Transducer Interface Serial Port Receive Decoder Filter Gain PCM 2.05dB steps) in Transmit Filter PCM Transmit Filter Encoder Gain Gain -2.05dB ...
Page 6
... The COMMAND/ADDRESS byte contains: Figure 5 - Serial Port Relative Timing for Motorola Mode 00/National Microwire 84 Flexible Digital Interface A serial link is required to transport data between the MT9160B/61B and an external digital transmission device. The MT9160B/61B utilizes the ST-BUS architecture defined by Zarlink Semiconductor but DATA INPUT/OUTPUT ...
Page 7
Advance Information F0i DSTi, CHANNEL 0 CHANNEL 1 D-channel C-channel DSTo LSB first MSB first for C, B1- & B2- for D- Channel F0od also supports a strobed data interface found on many standard Codec devices. This interface is commonly ...
Page 8
MT9160B/61B DEN: When 1, ST-BUS D-channel data ( bits/frame depending on the state of the D8 bit) is shifted into/ out of the D-channel (READ/WRITE) register. When 0, the receive D-channel data (READ) is still shifted into the ...
Page 9
Advance Information IRQ FP n-3 n-2 DSTo/ DSTi Di-bit Group I II Receive D-Channel No preset value * note that frame n+4 is equivalent to frame n of the next cycle. FP C4i C2 DSTo/ D0 ...
Page 10
MT9160B/61B SSI Mode The SSI BUS consists of input and output serial data streams named Din and Dout respectively, a Clock input signal (CLOCKin), a framing strobe input (STB) and the MT9161B provides a delayed framing strobe output (STBd). The ...
Page 11
MT9160B/61B Register Summary Address Bit 7 Bit 6 00 RxINC RxFG RxFG PDFDI PDDR 04 CEN DEN 07y - - Table 2 ...
Page 12
Advance Information Gain Control Register Side-tone Gain Setting (dB) (default) OFF -9.96 -6.64 -3.32 0 3.32 6.64 9.96 STG = Side-tone Gain bit n n Path Control - - - ...
Page 13
MT9160B/61B Control Register 1 PDFDI PDDR Rst PDFDI When high, the FDI PLA and the Filter/Codec are powered down. When low, the FDI is active (default). PDDR When high, the ear driver and Filter/Codec are powered down. ...
Page 14
Advance Information C-Channel Register Micro-port access to the ST-BUS C-Channel information read and write D-Channel Register D7-D0 Data written to this register will be transmitted every frame, in ...
Page 15
MT9160B/61B Applications Figure 9 shows an application in a digital phone set. Various configurations of pair gain drops are depicted in Figures 12a and 12b using the MT9125 and MT9126, respectively. 330 + 0.1 F 511 100K ...
Page 16
Advance Information VBias 0 0.1 F 0.1 F 100K +5V A/ /IRQ INTEL CS MCS-51 or SCLK MOTOROLA SPI DATA1 Micro- DATA2 Controller DATA2 Motorola Mode only l From Digita Phone Twisted Pair VBias 0 ...
Page 17
MT9160B/61B Absolute Maximum Ratings Parameter 1 Supply Voltage 2 Voltage on any I/O pin 3 Current on any I/O pin (transducers excluded) 4 Storage Temperature 5 Power Dissipation (package) † Exceeding these values may cause permanent damage. Functional operation under ...
Page 18
Advance Information DC Electrical Characteristics Characteristics 1 Input HIGH Voltage CMOS inputs 2 Input LOW Voltage CMOS inputs 3 VBias Voltage Output 4 V Output Voltage Ref 5 Input Leakage Current 6 Positive Going Threshold Voltage (PWRST only) Negative Going ...
Page 19
MT9160B/61B † AC Characteristics for A/D (Transmit) Path - 3.14dB =1.843V for A-Law, at the Codec (V rms Characteristics 1 Analog input equivalent to overload decision 2 Absolute half-channel gain M to Dout Tolerance at all other transmit filter settings ...
Page 20
Advance Information † AC Characteristics for D/A (Receive) Path 3.14dB =1.843V for A-Law, at the Codec. (V rms Characteristics 1 Analog output at the Codec full scale 2 Absolute half-channel gain. Din to HSPKR Tolerance at all other receive filter ...
Page 21
MT9160B/61B AC Electrical Characteristics Characteristics 1 Absolute path gain gain adjust = 0dB 2 Tolerance of other side-tone settings (-9.96 to 9.96 dB) relative to output at 0dB setting † AC Electrical Characteristics are over recommended temperature range & recommended ...
Page 22
Advance Information AC Electrical Characteristics Characteristics 1 C4i Clock Period 2 C4i Clock High period 3 C4i Clock Low period 4 C4i Clock Transition Time 5 F0i Frame Pulse Setup Time 6 F0i Frame Pulse Hold Time 7 Delayed Frame ...
Page 23
MT9160B/61B AC Electrical Characteristics Characteristics 1 BCL Clock Period 2 BCL Pulse Width High 3 BCL Pulse Width Low 4 BCL Rise/Fall Time 5 Strobe Pulse Width 6 Delayed Strobe Pulse Width 7 Strobe setup time before BCL falling 8 ...
Page 24
Advance Information t t BCLH t R CLOCKin 70% (BCL) 30% t DIS 70% Din 30% t DOZL 70% Dout 30% t DOZH 70% STB 30% 70% STBd 30% Figure 12 - SSI Synchronous Timing Diagram AC Electrical Characteristics Characteristics ...
Page 25
MT9160B/61B 70% STB 30% t dda2 t dha1 t dda1 70% Dout Bit 1 30% T DATA1 70% Din D1 30 DATA Figure 13 - SSI Asynchronous Timing Diagram AC Electrical Characteristics Characteristics 1 ...
Page 26
Advance Information 2.0V 0.8V t IDS t IDH t CH SCLK t CSSI CS t CSSM t CH SCLK IDH t IDS 2.0V 0.8V Intel® and MCS-51® are registered trademarks of Intel Corporation Motorola® and SPI® are ...
Page 27
...
Page 28
...
Page 29
...
Page 30
... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...