MT9160BE Zarlink Semiconductor, MT9160BE Datasheet - Page 2

• Manufacturer Part Number: MT9160BE
• Description: Description = 5V Multi-featured Phone Codec With Programmable U/a Law Companding ;; Package Type = Pdip ;; No. Of Pins = 24
• Manufacturer: Zarlink Semiconductor

MT9160B/61B
Pin Description
80
Pin #
20 Pin
PWRST
A/ /IRQ
DATA1
DATA2
VSSD
10
11
12
SCLK
VBias
1
2
3
4
5
6
7
8
9
VRef
CS
IC
Pin #
24 Pin
20 PIN SOIC/SSOP
10
10
11
12
13
14
1
2
3
4
5
6
7
8
9
MT9160BS/BN
1
2
4
5
6
7
8
PWRST Power-up Reset (Input). CMOS compatible input with Schmitt Trigger (active low).
A/ /IRQ A/ - When internal control bit DEn = 0 this CMOS level compatible input pin
DATA 1
DATA 2
Name
SCLK
V
V
V
D
CS
D
20
19
18
17
16
15
14
13
12
11
Bias
IC
SSD
Ref
out
in
M +
M -
VSSA
VDD
CLOCKin
STB/F0i
Din
Dout
HSPKR +
HSPKR -
Bias Voltage (Output). (V
amplifiers. Connect 0.1 F capacitor to V
Reference Voltage for Codec (Output). Nominally [(V
internally. Connect 0.1 F capacitor to V
Resets internal state of device.
Internal Connection. Tie externally to V
governs the companding law used by the filter/Codec; -Law when tied to V
A-Law when tied to V
IRQ - When internal control bit DEn = 1 this pin becomes an open-drain interrupt
output signalling valid access to the D-Channel registers in ST-BUS mode.
Digital Ground. Nominally 0 volts.
Chip Select (Input). This input signal is used to select the device for microport
data transfers. Active low. CMOS level compatible.
Serial Port Synchronous Clock (Input). Data clock for microport. CMOS level
compatible.
Bidirectional Serial Data. Port for microprocessor serial data transfer. In Motorola/
National mode of operation, this pin becomes the data transmit pin only and data
receive is performed on the DATA 2 pin. Input CMOS level compatible.
Serial Data Receive. In Motorola/National mode of operation, this pin is used for
data receive. In Intel mode, serial data transmit and receive are performed on the
DATA 1 pin and DATA 2 is disconnected. Input CMOS level compatible.
Data Output. A high impedance three-state digital output for 8 bit wide channel
data being sent to the Layer 1 transceiver. Data is shifted out via this pin concurrent
with the rising edge of the bit clock during the timeslot defined by STB, or according
to standard ST-BUS timing.
Data Input. A digital input for 8 bit wide channel data received from the Layer 1
transceiver. Data is sampled on the falling edge of the bit clock during the timeslot
defined by STB, or according to standard ST-BUS timing. Input level is CMOS
compatible.
A/ /IRQ
DATA1
DATA2
PWRST
VSSD
SCLK
VBias
VRef
NC
NC
CS
IC
Figure 2 - Pin Connections
10
11
12
1
2
3
4
5
6
7
8
9
24 PIN PDIP
MT9160BE
DD
. Logically OR’ed with A/ register bit.
DD
24
23
22
21
20
19
18
17
16
15
14
13
/2) volts is available at this pin for biasing external
Description
M +
M -
VSSA
NC
HSPKR +
HSPKR -
VDD
CLOCKin
NC
STB/F0i
Din
Dout
SSA,
SSA,
SSD
Connect 1 F capacitor to VBias.
Connect 1 F capacitor to Vref.
for normal operation.
PWRST
A/ /IRQ
DATA1
DATA2
VSSD
VBias
SCLK
VRef
NC
NC
CS
IC
24 PIN PDIP/SOIC/SSOP
Advance Information
MT9161BE/BS/BN
DD
10
11
12
1
2
3
4
5
6
7
8
9
/2)-1.9] volts. Used
24
23
22
21
20
19
18
17
16
15
14
13
M +
M -
VSSA
NC
HSPKR +
HSPKR -
VDD
CLOCKin
STBd/FOod
STB/F0i
Din
Dout
SSD
and